公开(公告)号：GB2606906B

公开(公告)日：2025-05-14

申请号：GB202209607

申请日：2020-11-13

Applicant: IBM

Inventor： MOHIT KARVE ,  BRIAN THOMPTO

IPC: G06F12/0864 ,  G06F12/0882 ,  G06F12/1009 ,  G06F12/1036 ,  G06F13/16

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.

公开(公告)号：GB2603653A

公开(公告)日：2022-08-10

申请号：GB202202229

申请日：2020-07-21

Applicant: IBM

Inventor： BRIAN THOMPTO ,  MAARTEN BOERSMA ,  ANDREAS WAGNER ,  JOSE EDUARDO MOREIRA ,  HUNG LE ,  SILVIA MELITTA MUELLER ,  DUNG NGUYEN

IPC: G06F9/30

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

公开(公告)号：GB2606906A

公开(公告)日：2022-11-23

申请号：GB202209607

申请日：2020-11-13

Applicant: IBM

Inventor： MOHIT KARVE ,  BRIAN THOMPTO

IPC: G06F12/0864

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.