公开(公告)号：GB2606906B

公开(公告)日：2025-05-14

申请号：GB202209607

申请日：2020-11-13

Applicant: IBM

Inventor： MOHIT KARVE ,  BRIAN THOMPTO

IPC: G06F12/0864 ,  G06F12/0882 ,  G06F12/1009 ,  G06F12/1036 ,  G06F13/16

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.

公开(公告)号：GB2628249B

公开(公告)日：2025-02-12

申请号：GB202408070

申请日：2022-10-08

Applicant: IBM

Inventor： AARON DINGLER ,  MOHIT KARVE ,  ALPER BUYUKTOSUNOGLU

IPC: G06F12/121 ,  G06F12/08

Abstract: A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.

公开(公告)号：GB2604205A

公开(公告)日：2022-08-31

申请号：GB202114291

申请日：2021-10-06

Applicant: IBM

Inventor： MOHIT KARVE ,  NAGA P GORTI

IPC: G06F12/0862

Abstract: A method, comprises predicting a candidate address, calculating a hash of the candidate address, checking a first Bloom filter based on the hash, and determining, based on the checking, to prefetch information stored at the candidate address. The predicting may include predicting a second candidate address, calculating a second hash of the second candidate address, checking the first Bloom filter based on the second hash, and determining, based on the checking, that prefetching second information stored at the second candidate address is unnecessary. The predicting may also include determining a first address of a cache hit and determining the candidate address based on the first address. The checking may include comparing the first Bloom filter and a second Bloom filter, generating a result vector based on the comparison, and checking the result vector. The method may include detecting a cache write and updating, based on the hash, a value of the first Bloom filter and the second Bloom filter, e.g. incrementing the value. The method may further comprise periodically flushing the first Bloom filter and the second Bloom filter, wherein the flushing of the first Bloom filter is offset from the flushing of the second Bloom filter.

公开(公告)号：GB2606906A

公开(公告)日：2022-11-23

申请号：GB202209607

申请日：2020-11-13

Applicant: IBM

Inventor： MOHIT KARVE ,  BRIAN THOMPTO

IPC: G06F12/0864

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.