公开(公告)号：DE2966357D1

公开(公告)日：1983-12-01

申请号：DE2966357

申请日：1979-11-19

Applicant: IBM

Inventor： SCHETTLER HELMUT ,  BROSCH RUDOLF DR ,  ZUEHLKE RAINER DR ,  SCHUMACHER HANS DR

IPC: H03K19/0175 ,  G05F1/46 ,  H03K5/00 ,  H03K5/13

Abstract: For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times. The digital control circuit comprises a comparator circuit where the signal delay of a clock pulse is compared in a chain of inverters with the very precisely defined clock interval. Depending on the result of the comparison, the count of an up-down counter is incremented or decremented by one. The resulting count is decoded and converted into a corresponding voltage for operating the circuits of the semiconductor chip. Subsequently, the above described steps are repeated until the difference DELTA t between the arrival of a clock pulse delayed by the chain, and the following undelayed clock pulse approaches zero.