公开(公告)号：JP2002132500A

公开(公告)日：2002-05-10

申请号：JP2001282724

申请日：2001-09-18

Applicant: IBM

Inventor： BRUCE C JAMEY ,  MARK A CHECK ,  LIPTAY JOHN S

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method of detecting an address generating interlock and its system in a pipeline data processor. SOLUTION: A step accumulating a plurality of vectors over predefined numbers of a processor clock cycle and following vectors are responded to following clock cycles in the method. The method is comprised of a step accumulating status of all-purpose registers with one and more in a plurality of vectors having the same bit position concerning to each vector of a plurality of the vectors corresponding to specific all-purpose registers, a step generating a list for renewal of reserved all-purpose registers in logic combination of a plurality of vectors, and a step discriminating existence of the address generating interlock from the list for renewal of reserved all-purpose register.