公开(公告)号：JP2002132500A

公开(公告)日：2002-05-10

申请号：JP2001282724

申请日：2001-09-18

Applicant: IBM

Inventor： BRUCE C JAMEY ,  MARK A CHECK ,  LIPTAY JOHN S

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method of detecting an address generating interlock and its system in a pipeline data processor. SOLUTION: A step accumulating a plurality of vectors over predefined numbers of a processor clock cycle and following vectors are responded to following clock cycles in the method. The method is comprised of a step accumulating status of all-purpose registers with one and more in a plurality of vectors having the same bit position concerning to each vector of a plurality of the vectors corresponding to specific all-purpose registers, a step generating a list for renewal of reserved all-purpose registers in logic combination of a plurality of vectors, and a step discriminating existence of the address generating interlock from the list for renewal of reserved all-purpose register.

公开(公告)号：JP2000029684A

公开(公告)日：2000-01-28

申请号：JP11475699

申请日：1999-04-22

Applicant: IBM

Inventor： MARK A CHECK ,  RONALD M SMITH ,  JOHN S RIPTY ,  ERIK M SCHWARZ ,  TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To support a high-frequency operation by arranging the extension of an operation code outside the starting four bytes of an instruction format and assigning a code so that a machine can determine the accurate format of an instruction with only starting light bits of the code. SOLUTION: As for a base register 18, a multiplexer selector 19 directly controls a base multiplexer 20 and selects and sends a default base position to a CPR register file 15. A 2nd base register is gated from an instruction text to a B prime slot in the base register 18 in a 1st cycle and the multiplexer selector 19 is set to 1. A critical path, therefore, reaches a register for an address adder 16 from the base register 18 through the multiplexer 20 controlled by the selector 19 and the GPR register file 15. Thus, combination logic is excluded from the critical path.

公开(公告)号：JP2000099325A

公开(公告)日：2000-04-07

申请号：JP11055499

申请日：1999-04-19

Applicant: IBM

Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a computer which has a millimode function for a system that has a central processor and also has operations of both normal mode and millimode. SOLUTION: This computer system having a millimode function gives the control to a millicode to continue a BHT(branch history table) operation excluding a case where a special situation occurs to need the control of an instruction fetch operation. A BHT 5 can be turned off to a certain section for execution of a code and cannot be disabled to all sections. A single free-running BHT functions to both normal mode and millimode used for a central processor that can be executed in a millimode by the BHT which indicates an instruction fetch containing both global BHT and millicode disabling functions.

公开(公告)号：JP2000029685A

公开(公告)日：2000-01-28

申请号：JP11477199

申请日：1999-04-22

Applicant: IBM

Inventor： MARK A CHECK ,  RONALD M SMITH ,  JOHN S RIPTY ,  ERIK M SCHWARZ ,  TIMOTHY J SLEEGAL ,  CHARLES F WEBB

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To enable a foating-point processor to determine the accurate format of an instruction by determining that an instruction is in 2nd format by decoding an operation code and gating information needed for address generation to an adder according to the decision result. SOLUTION: A 2nd base register is gated from an instruction text to a B prime slot in a base register 18 in a 1st cycle and a multiplexer selector 19 is set to 1. A critical path, therefore, reaches a register for an address adder 16 from the base register 18 through a multiplexer 20 controlled by the selector 19 and a GPR file 15. In this case, the floating-point processor decodes a 1st part of the operation code to determine that the instruction is in 2nd format, and gates information needed for address generation to the adder 16 according to the determination result.

公开(公告)号：JP2003216490A

公开(公告)日：2003-07-31

申请号：JP2002371417

申请日：2002-12-24

Applicant: IBM

Inventor： LIPTAY LYNNE M ,  MARK A CHECK ,  MARK S FARRELL ,  GIAMEI BRUCE C ,  CHARLES F WEBB

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To provide a method for ensuring that a line is present in an instruction cache by instructing a computing system. SOLUTION: In the method for ensuring that the line is present in the instruction cache by instructing the computing system, a line-touch instruction is selected, the line-touch instruction is recognized as one type of a branch instruction which does not branch, the line-touch instruction is executed to fetch a target line from a target address into the instruction cache, and execution of the line-touch instruction is interlocked by completion of the fetch of the target line for preventing execution of an instruction following the line-touch instruction until the target line reaches the cache. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000112753A

公开(公告)日：2000-04-21

申请号：JP11053699

申请日：1999-04-19

Applicant: IBM

Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To obtain a method for operating a computer that has a milli-mode function by giving control, that enables a BHT operation to continue, to a milli-code except in the case of a specific situation where the control of an instruction fetch operation is needed. SOLUTION: A searching means 6 supplies a start address that is used when a branch history table(BHT) 5 accesses a BHT array 8 to the table (BHT) 5 which supplies information that gives an instruction to an instruction fetching means 2. Target information is latched in a register 10, and instruction address information is compared with a search address by a comparator 9. Results of the instruction address comparator 9 and a global disable latch 13 are used to decide if hit takes place and which set is desirable in hit detection logic 12. The selection of the set is used to control a multiplexer 11 and to make the instruction fetching means 2 gate correct branch target information.