公开(公告)号：EP2399105A4

公开(公告)日：2018-01-10

申请号：EP10744347

申请日：2010-02-19

Applicant: IBM

Inventor： BRUNNER TIMOTHY A ,  MCINTYRE GREGORY R

IPC: G01J4/04 ,  G03F1/44 ,  G03F7/20 ,  G06F17/50

CPC classification number: G06F17/50 ,  G01J4/04 ,  G03F1/44 ,  G03F7/70466 ,  G03F7/70566

Abstract: This invention relates to the manufacture of semiconductor substrates such as wafers and to a method for monitoring the state of polarization incident on a photomask in projection printing using a specially designed polarization monitoring reticle for high numerical aperture lithographic scanners. The reticle measures 25 locations across the slit and is designed for numerical apertures above 0.85. The monitors provide a large polarization dependent signal which is more sensitive to polarization. A double exposure method is also provided using two reticles where the first reticle contains the polarization monitors, clear field reference regions and low dose alignment marks. The second reticle contains the standard alignment marks and labels. For a single exposure method, a tri-PSF low dose alignment mark is used. The reticles also provide for electromagnetic bias wherein each edge is biased depending on that edge's etch depth.

公开(公告)号：JP2007243177A

公开(公告)日：2007-09-20

申请号：JP2007040403

申请日：2007-02-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRUNNER TIMOTHY A ,  LIEBMANN LARS WOLFGANG ,  CULP JAMES A

IPC: H01L21/28 ,  H01L21/027 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/28123

Abstract: PROBLEM TO BE SOLVED: To provide a double exposure double resist layer process for forming gate patterns.
SOLUTION: The method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于形成栅极图案的双曝光双光刻胶层工艺。 解决方案：形成平面CMOS晶体管的方法将形成栅极层的步骤划分为用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤 。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后利用栅极焊盘和局部互连的图案蚀刻多晶硅，由此减少来自不同曝光区域的衍射数量和其它串扰。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2008191656A

公开(公告)日：2008-08-21

申请号：JP2008001453

申请日：2008-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRUNNER TIMOTHY A ,  HIBBS MICHAEL S

IPC: G03F1/14 ,  H01L21/027

CPC classification number: G03F1/62 ,  G03F7/11 ,  Y10T428/24

Abstract: PROBLEM TO BE SOLVED: To provide an optical pellicle to protect a photomask from particulate contamination during semiconductor lithography which has enhanced transparency and operational characteristics. SOLUTION: The pellicle utilizes alternating layers of a transparent polymer and a transparent inorganic layer to form pellicles which have high transmission properties and high strength. In a preferred pellicle, a three-layer pellicle is provided having a transparent inorganic layer 4 sandwiched between two polymer layers 12a and 12b. A five-layer pellicle is also provided with the outer layers and a middle layer being polymer layers and the inner layers an inorganic material. The preferred polymer layer is a perfluorinated polymer such as Teflon (R) and the preferred inorganic material is silicon dioxide. The pellicle of the invention provides light transmission of greater than 0.99% at incident light angles up to arcsine 0.45. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种光学防护薄膜，以保护光掩模免受半导体光刻期间的颗粒污染，这具有增强的透明度和操作特性。 解决方案：防护薄膜组件利用透明聚合物和透明无机层的交替层来形成具有高透射性和高强度的薄膜。 在优选的防护薄膜组件中，提供三层薄膜，其具有夹在两个聚合物层12a和12b之间的透明无机层4。 五层防护薄膜也设有外层，中间层是聚合物层，内层是无机材料。 优选的聚合物层是全氟化聚合物，例如Teflon，优选的无机材料是二氧化硅。 本发明的防护薄膜组件在入射光角直至反正弦0.45时提供大于0.99％的透光率。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JPH11150115A

公开(公告)日：1999-06-02

申请号：JP23172998

申请日：1998-08-18

Applicant: IBM

Inventor： CATHERINA E BEIVICH ,  BRUNNER TIMOTHY A ,  ALESSANDRO CAESAR CALEGARI ,  ALFRED GRILL ,  CHRISTOPHER V JARNES ,  BISHUNABAI VITTARUBAI PATEL

IPC: C01B31/00 ,  C23C14/06 ,  G03F7/11 ,  H01L21/027 ,  H01L21/3205

Abstract: PROBLEM TO BE SOLVED: To form a resist which has superior optical purity and high adjustability and consists of a plurality of layers by forming an antireflection film on a substrate through vapor deposition. SOLUTION: After an amorphous carbon film a-C:X:H containing hydrogen and fluoride is stuck to a substrate by plasma-intensified chemical gaseous-phase vapor deposition, a photoresist PR containing silicon is applied to the surface of the carbon film a-C:X:H with a spin coater and baked. Then, after the photoresist PR has been developed with a developing solution, the carbon film a-C:X:H is subjected to reactive ion etching in oxygen plasma. As a result, the carbon film a-C:X:H functions as an ideal thick planarized lower antireflection film in a two-layer resist system for ultraviolet and far-infrared rays and can improve line width control and the performance of an integrated circuit.