公开(公告)号：JP2003051549A

公开(公告)日：2003-02-21

申请号：JP2002162321

申请日：2002-06-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BALLANTINE ARNE W ,  BUCHANAN DOUGLAS A ,  CARTIER EDUARD A ,  COOLBAUGH DOUGLAS D ,  GOUSEV EVGENI P ,  OKORN-SCHMIDT HARALD F

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/28 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/51 ,  H01L29/94

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor.
SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了提供诸如多晶硅 - 多晶硅电容器和MIS电容器的FEOL电容器，其电容率k高于约8的高介电常数（高k）电介质可以组装在电容器结构中，以及用于 制造FEOL电容。 解决方案：首先，通过使用离子注入在含Si衬底10中形成下电极12。 介电常数k大于约8的高介电常数电介质14形成在下电极12的至少一部分上。由高介电常数电介质形成由本征基极多晶硅层构成的双极器件的掺杂Si含电极16 通过执行上述处理，可以获得MIS电容器。 通过该方法，形成其中串联电阻小的上电极和下电极的FEOL电容器，每单位面积的电容量大，并且可以获得高的频率响应特性。 此外，芯片尺寸可以显着降低，特别是在使用大面积的电容器的模拟信号和混合信号的使用中，芯片尺寸可以显着降低。

公开(公告)号：CA1283490C

公开(公告)日：1991-04-23

申请号：CA600747

申请日：1989-05-25

Applicant: IBM

Inventor： BUCHANAN DOUGLAS A ,  CALLEGARI ALESSANDRO C ,  HOH PETER D ,  LACEY DIANNE L

IPC: H01L21/318 ,  H01L29/78 ,  H01L21/70 ,  H01L27/04

Abstract: METHOD FOR PASSIVATING A COMPOUND SEMICONDUCTOR SURFACE AND DEVICE HAVING IMPROVED SEMICONDUCTOR-INSULATOR INTERFACE A method for passivating the surface of a compound semiconductor comprises annealing the substrate to form an anion rich surface layer containing cationic and anionic oxides and stripping the oxides to leave only a very thin anionic layer on the surface. The substrate is then subjected to an H2 plasma cleaning to remove chemisorbed oxygen. An N2 plasma cleaning is then performed to form an anionic nitride layer that is free of any cationic nitride. A layer of insulating material, such as, a native or other oxide, or a nitride, is deposited. The resulting structure has a very low interface state density such that the Fermi level may be swept through the entire band gap.