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    METHOD FOR ETCHING SEMICONDUCTOR DEVICE
    1.
    发明专利
    METHOD FOR ETCHING SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH1064889A

    公开(公告)日：1998-03-06

    申请号：JP12258397

    申请日：1997-05-13

    Applicant: IBM ,  SIEMENS AG ,  TOSHIBA CORP

    Inventor： HOH PETER D ,  OIWA NORIHISA ,  GREWAL VIRINDER ,  SPULER BRUNO ,  KOCON WALDEMAR ,  WILTSHIRE GUADALUPE

    IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L49/00

    Abstract: PROBLEM TO BE SOLVED: To etch a pattern in the metallic silicide film within composite material by bringing the metallic silicide film into contact with the plasma being created by the mixed gas flow of HCl and Cl2 where the flow ratio HCl:Cl2 is set in the specified range. SOLUTION: The etching process includes etching a metallic silicide layer at a higher rate than that of the polysilicon layer within the composite material of the metallic silicide and polysilicon, and in this etching process, the metallic silicide film is brought into contact with the plasma being created by the mixed gas flow of HCl and Cl2 where the volume flow ratio HCl:Cl2 is set in the range of 3:1 to 6:1. Hereby, the pattern within the metallic silicide layer within the composite material of metallic silicide and polysilicon can be etched.

    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method
    2.
    发明专利
    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method 审中-公开
    集成电路金属外壳中应力减小的方法和使用该方法生产的集成电路

    公开(公告)号：JPH11274158A

    公开(公告)日：1999-10-08

    申请号：JP4899

    申请日：1999-01-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
    SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

    PROCESS FOR FORMING THE RIDGE STRUCTURE OF A SELF-ALIGNED SEMICONDUCTOR LASER
    4.
    发明专利
    PROCESS FOR FORMING THE RIDGE STRUCTURE OF A SELF-ALIGNED SEMICONDUCTOR LASER 未知

    公开(公告)号：CA2039875C

    公开(公告)日：1994-05-03

    申请号：CA2039875

    申请日：1991-04-05

    Applicant: IBM

    Inventor： WEBB DAVID J ,  HEUBERGER WILHELM ,  HARDER CHRISTOPH S ,  HOH PETER D

    IPC: H01S5/00 ,  H01L21/318 ,  H01S5/22 ,  H01S3/025

    Abstract: A process for forming the ridge structure of a self-aligned semiconductor laser, particularly useful for long wavelength devices as required for signal transmission systems. Described is the process as applied to an InP-system, double heterostructure (DH) laser. A thin Si3N4 layer (41) is inserted between the photoresist mask (42) that defines the ridge structure, and the contact layer (35). This results in improved adhesion and reduced etch undercutting whereby the ohmic contact area is increased, heat development decreased and device properties improved. Using a Si3N4 layer (41) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si3N4 layer (43) for device embedding, provides for the etch selectivity required in the process stepthat is used to expose the contact layer to ohmic contact metallization deposition.

    METHOD FOR PASSIVATING A COMPOUND SEMICONDUCTOR SURFACE AND DEVICE HAVING IMPROVED SEMICONDUCTOR- INSULATOR INTERFACE
    5.
    发明专利
    METHOD FOR PASSIVATING A COMPOUND SEMICONDUCTOR SURFACE AND DEVICE HAVING IMPROVED SEMICONDUCTOR- INSULATOR INTERFACE 未知

    公开(公告)号：CA1283490C

    公开(公告)日：1991-04-23

    申请号：CA600747

    申请日：1989-05-25

    Applicant: IBM

    Inventor： BUCHANAN DOUGLAS A ,  CALLEGARI ALESSANDRO C ,  HOH PETER D ,  LACEY DIANNE L

    IPC: H01L21/318 ,  H01L29/78 ,  H01L21/70 ,  H01L27/04

    Abstract: METHOD FOR PASSIVATING A COMPOUND SEMICONDUCTOR SURFACE AND DEVICE HAVING IMPROVED SEMICONDUCTOR-INSULATOR INTERFACE A method for passivating the surface of a compound semiconductor comprises annealing the substrate to form an anion rich surface layer containing cationic and anionic oxides and stripping the oxides to leave only a very thin anionic layer on the surface. The substrate is then subjected to an H2 plasma cleaning to remove chemisorbed oxygen. An N2 plasma cleaning is then performed to form an anionic nitride layer that is free of any cationic nitride. A layer of insulating material, such as, a native or other oxide, or a nitride, is deposited. The resulting structure has a very low interface state density such that the Fermi level may be swept through the entire band gap.

    PROCESS FOR FORMING THE RIDGE STRUCTURE OF A SELF-ALIGNED SEMICONDUCTOR LASER
    7.
    发明专利
    PROCESS FOR FORMING THE RIDGE STRUCTURE OF A SELF-ALIGNED SEMICONDUCTOR LASER 未知

    公开(公告)号：CA2039875A1

    公开(公告)日：1991-10-07

    申请号：CA2039875

    申请日：1991-04-05

    Applicant: IBM

    Inventor： WEBB DAVID J ,  HEUBERGER WILHELM ,  HARDER CHRISTOPH S ,  HOH PETER D

    IPC: H01S5/00 ,  H01L21/318 ,  H01S5/22 ,  H01S3/025

    Abstract: A process for forming the ridge structure of a self-aligned semiconductor laser, particularly useful for long wavelength devices as required for signal transmission systems. Described is the process as applied to an InP-system, double heterostructure (DH) laser. A thin Si3N4 layer (41) is inserted between the photoresist mask (42) that defines the ridge structure, and the contact layer (35). This results in improved adhesion and reduced etch undercutting whereby the ohmic contact area is increased, heat development decreased and device properties improved. Using a Si3N4 layer (41) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si3N4 layer (43) for device embedding, provides for the etch selectivity required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

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