公开(公告)号：US3662188A

公开(公告)日：1972-05-09

申请号：US3662188D

申请日：1970-09-28

Applicant: IBM

Inventor： WILLIAMS THOMAS A

IPC: H03K19/096 ,  H03K19/08

CPC classification number: H03K19/096

Abstract: A buffer circuit for interfacing multi-phase dynamic field effect transistor (FET) logic circuits with conventional logic circuits by converting pulsating logic signals to steady-state logic signals. A sampling stage gates the true and complement phases of the pulsating signal at an equilibrium state, thereby converting the pulsating signal to a steady-state level. An output stage detects the steady-state level and provides the output drive. The buffer is fabricated in accordance with FET technology and is placed on the same monolithic chip with the multi-phase FET circuits. Circuits for generating true and complement phases of the pulsating signal are also disclosed.

Abstract translation: 一种用于通过将脉动逻辑信号转换为稳态逻辑信号来将多相动态场效应晶体管（FET）逻辑电路与常规逻辑电路接口的缓冲电路。 采样级在平衡状态下对脉动信号的真相和补码相进行门控，从而将脉动信号转换为稳态电平。 输出级检测稳态电平并提供输出驱动。 缓冲器根据FET技术制造，并与多相FET电路放置在相同的单片芯片上。 还公开了用于产生脉动信号的真和补相位的电路。

公开(公告)号：DE3071936D1

公开(公告)日：1987-04-30

申请号：DE3071936

申请日：1980-12-16

Applicant: IBM

Inventor： DE LA MONEDA FRANCISCO H ,  WILLIAMS THOMAS A

IPC: G11C17/00 ,  G11C11/41 ,  G11C17/08 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8246 ,  H01L23/52 ,  H01L23/528 ,  H01L27/112 ,  H01L27/118 ,  H01L29/78

公开(公告)号：IT7925852D0

公开(公告)日：1979-09-20

申请号：IT2585279

申请日：1979-09-20

Applicant: IBM

Inventor： BULA JOHN ,  BERTIN CLAUDE L ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/12 ,  G11C17/00 ,  H01L23/525 ,  G11C

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

公开(公告)号：IT1165312B

公开(公告)日：1987-04-22

申请号：IT2585279

申请日：1979-09-20

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  BULA JOHN ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/12 ,  H01L23/525 ,  G11C17/00 ,  G11C

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

公开(公告)号：DE2965440D1

公开(公告)日：1983-07-07

申请号：DE2965440

申请日：1979-08-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  BULA JOHN ,  MARTIN LARRY C ,  WILLIAMS THOMAS A

IPC: G11C17/00 ,  G11C17/12 ,  H01L23/525

Abstract: Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.