公开(公告)号：DE2861103D1

公开(公告)日：1981-12-03

申请号：DE2861103

申请日：1978-12-16

Applicant: IBM

Inventor： CADE PAUL EDMAND

IPC: G01J1/02 ,  H01L27/144 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/103 ,  H01L27/14 ,  H01L31/02

公开(公告)号：DE3579879D1

公开(公告)日：1990-10-31

申请号：DE3579879

申请日：1985-07-23

Applicant: IBM

Inventor： BERGENDAHL ALBERT STEPHEN ,  CADE PAUL EDMAND ,  LUECKE FRANCIS STEPHEN ,  PETERSEN KURT EDWARD ,  GONNELLA NORMAN THOMAS

IPC: G11B7/26 ,  G11B23/00

公开(公告)号：DE3563148D1

公开(公告)日：1988-07-07

申请号：DE3563148

申请日：1985-06-03

Applicant: IBM

Inventor： CADE PAUL EDMAND

IPC: G03F9/00 ,  H01L21/027 ,  H01L21/268 ,  H01L23/544 ,  H01L23/54

公开(公告)号：DE3170741D1

公开(公告)日：1985-07-04

申请号：DE3170741

申请日：1981-10-09

Applicant: IBM

Inventor： CADE PAUL EDMAND

IPC: G01P15/08 ,  G01P15/125 ,  G02B6/12 ,  G02B26/08 ,  G02B26/10 ,  G02F1/19 ,  G09F9/37 ,  G11C11/00 ,  G11C11/42 ,  G11C13/04 ,  H01H59/00 ,  H01L21/331 ,  H01L21/822 ,  H01L27/04 ,  H01L29/73 ,  G02F1/31

Abstract: A dual electrode electrostatically deflectable deformographic switch is driven by co-incident voltages and can be made to display and store information. It comprises a substrate (10) with at least one opening (13), a cantilevered beam (12) supported over said opening (13), means for impressing a selective voltage on the substrate (10), a pair of conductive leads (14, 15) on said beam (12), means for applying selected voltages on each of said leads (14, 15) to electrically deflect the beam (12) with respect to the substrate (10), and means for reducing said selected voltage to a standby level sufficient to maintain said deflected beam (12) in said deflected position. Only two voltage levels above ground, i.e., a write voltage and a standby voltage, are required. The switch will enable copiers to be directly driven by computers. The switch can also be used as an optical waveguide transmit/receive switch or an accelerometer.

公开(公告)号：DE2632036A1

公开(公告)日：1977-03-31

申请号：DE2632036

申请日：1976-07-16

Applicant: IBM

Inventor： CADE PAUL EDMAND

IPC: G11C17/00 ,  G11C11/35 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/098 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L29/808 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78

Abstract: The present invention relates to an integrated memory system comprising an array of depletion mode field effect transistors operated in a common control electrode mode to provide an array with the density of metal oxide semiconductor field effect transistor arrays and the speed of bipolar transistor arrays. Each transistor of the array has a gate or control electrode surrounding a channel region of the device which gate is held at a reference potential with respect to the source and drain regions which are selectively biased.