公开(公告)号：EP1402573A4

公开(公告)日：2010-09-15

申请号：EP02741827

申请日：2002-06-04

Applicant: IBM

Inventor： CAMPBELL JOHN E ,  DEVINE WILLIAM T ,  SRIKRISHAN KRIS V

IPC: H01L21/84 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/78648 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10873 ,  H01L27/11803 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：CA1080366A

公开(公告)日：1980-06-24

申请号：CA281835

申请日：1977-06-30

Applicant: IBM

Inventor： CAMPBELL JOHN E ,  THOMPSON GERHARD R

IPC: G11C7/00 ,  G06F5/06 ,  G06F12/12 ,  H03M7/16 ,  G11C8/00

Abstract: FIRST IN - FIRST OUT MEMORY ARRAY CONTAINING SPECIAL BITS FOR REPLACEMENT ADDRESSING A first in - first out auxiliary memory array for storing binary data wherein each member (word) of the array includes a special bit which is used in combination with the special bits of the other members comprising the same member set to form the address of the next member whose data is to be replaced. Each member comprises an identifier field, a data field and the aforementioned special bit. When a member set is addressed, each member of the set is read to determine whether there is a match on the respective identifier field. If there is a match, the data field of the same member is utilized. If there is no match on the identifier field of any member of the addressed set, the main memory is accessed for the necessary replacement information which is to be written into the member which contains the oldest data. The address of the last-named member is determined by the exclusive ORing of the special bits of all the members comprising the given set. When the replacement data is written into the addressed member, the state of the special bit thereof is inverted. The inverted state of the special bit is written into the member simultaneously with the writing in of the replacement data.

公开(公告)号：FR2357036A1

公开(公告)日：1978-01-27

申请号：FR7717615

申请日：1977-06-02

Applicant: IBM

Inventor： CAMPBELL JOHN E ,  THOMPSON GERHARD R

IPC: G11C7/00 ,  G06F5/06 ,  G06F12/12 ,  H03M7/16 ,  G11C15/04

Abstract: 1533831 FIFO storage INTERNATIONAL BUSINESS MACHINES CORP 13 June 1977 [2 July 1976] 24608/77 Heading G4A Each storage area 0-7 has a marker bit a-h, an encoding (EXOR) circuit 10 produces from the marker bits an indication of which storage area was the first to be loaded, and each time a storage area is loaded its marker bit is inverted, whereby the encoding circuit identifies the storage areas in a predetermined cyclic sequence. The encoding circuit shown produces coded bit combinations ABC in Gray code sequence when the marker bits are set from 0 to 1 in the order a, b, d, c, g, h, f, e and are subsequently reset from 1 to 0 in the same order as successive storage areas are loaded (overwriting occurring after the first sequence). The FIFO store may form the cache memory of a multilevel storage system, the output of circuit 10 being decoded to select the storage area to receive replacement data from main storage when the requested data is not present in the cache.