公开(公告)号：EP1402573A4

公开(公告)日：2010-09-15

申请号：EP02741827

申请日：2002-06-04

Applicant: IBM

Inventor： CAMPBELL JOHN E ,  DEVINE WILLIAM T ,  SRIKRISHAN KRIS V

IPC: H01L21/84 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/78648 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10873 ,  H01L27/11803 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：DE2556275A1

公开(公告)日：1976-07-08

申请号：DE2556275

申请日：1975-12-13

Applicant: IBM

Inventor： COX DENNIS T ,  DEVINE WILLIAM T ,  KELLY GILBERT J

IPC: H01L27/00 ,  H01L27/112 ,  H03K19/177 ,  H03K19/00 ,  G06F7/38

公开(公告)号：FR2402973A1

公开(公告)日：1979-04-06

申请号：FR7822194

申请日：1978-07-21

Applicant: IBM

Inventor： DEVINE WILLIAM T ,  WASHBURN WILLIAM F

IPC: H03K19/017 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/20 ,  H03K19/30

Abstract: An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.

公开(公告)号：DE2556274A1

公开(公告)日：1976-07-08

申请号：DE2556274

申请日：1975-12-13

Applicant: IBM

Inventor： COX DENNIS T ,  DEVINE WILLIAM T ,  KELLY GILBERT J

IPC: H01L23/535 ,  H01L27/112 ,  H03K19/177 ,  H03K19/00 ,  G06F7/38

公开(公告)号：CA1047610A

公开(公告)日：1979-01-30

申请号：CA238824

申请日：1975-10-30

Applicant: IBM

Inventor： COX DENNIS T ,  DEVINE WILLIAM T ,  KELLY GILBERT J

IPC: H01L27/00 ,  H01L27/112 ,  H03K19/177 ,  H03K19/20

Abstract: HIGH DENSITY LOGIC ARRAY This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end. The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.

公开(公告)号：CA1045214A

公开(公告)日：1978-12-26

申请号：CA238823

申请日：1975-10-30

Applicant: IBM

Inventor： COX DENNIS T ,  DEVINE WILLIAM T ,  KELLY GILBERT J

IPC: H01L23/535 ,  H01L27/112 ,  H03K19/177 ,  H03K19/08

Abstract: This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.

公开(公告)号：FR2296967A1

公开(公告)日：1976-07-30

申请号：FR7534722

申请日：1975-11-05

Applicant: IBM

Inventor： COX DENNIS T ,  DEVINE WILLIAM T ,  KELLY GILBERT J

IPC: H01L27/00 ,  H01L27/112 ,  H03K19/177 ,  H03K19/20

Abstract: Logic switching circuits are provided at least at some crosspoints. They carry out ogic operations in accordance with interrogation signals applied to input wires. Interrogation circuits are provided at both ends of at least some of the input wires, so that two different interrogation signals can be applied to the same wire. Some of these input wires are divided in sections in orer to form two groups of mutually independent logic circuits so that two interrogation signals applied to the same inpu wire control only one group of logic switching circuits.