公开(公告)号：DE4032571A1

公开(公告)日：1991-05-02

申请号：DE4032571

申请日：1990-10-13

Applicant: IBM

Inventor： CAPPS JUN LOUIS BENNIE ,  FORSTER JIMMY GRANT ,  PRICE WILLIAM EVERETT ,  RUPE ROBERT WILLIAM ,  UPLINGER KENNETH ALLEN

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/16

Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.