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公开(公告)号：ZA9007497B
公开(公告)日：1991-06-26
申请号：ZA9007497
申请日：1990-09-19
Applicant: IBM
Inventor： CAPPS LOUIS BENNIE , LOUIS BENNIE CAPPS , PRICE WILLIAM EVERETT , WILLIAM EVERETT PRICE , UPLINGER KENNETH ALLEN , KENNETH ALLEN UPLINGER , FORSTER JIMMY GRANT , JIMMY GRANT FORSTER , RUPE ROBERT WILLIAM , ROBERT WILLIAM RUPE
CPC classification number: G06F11/1044 , G06F11/073 , G06F11/0772
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公开(公告)号：HK71596A
公开(公告)日：1996-05-03
申请号：HK71596
申请日：1996-04-25
Applicant: IBM
Inventor： CAPPS LOUIS BENNIE , FORSTER JIMMY GRANT , PRICE WILLIAM EVERETT , RUPE ROBERT WILLIAM , UPLINGER KENNETH ALLEN
Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.
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Patent Agency Ranking
公开(公告)号：DE69018365T2
公开(公告)日：1995-10-12
申请号：DE69018365
申请日：1990-09-11
Applicant: IBM
Inventor： CAPPS LOUIS BENNIE , FORSTER JIMMY GRANT , PRICE WILLIAM EVERETT , RUPE ROBERT WILLIAM , UPLINGER KENNETH ALLEN
Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.
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公开(公告)号：DE4032571A1
公开(公告)日：1991-05-02
申请号：DE4032571
申请日：1990-10-13
Applicant: IBM
Inventor： CAPPS JUN LOUIS BENNIE , FORSTER JIMMY GRANT , PRICE WILLIAM EVERETT , RUPE ROBERT WILLIAM , UPLINGER KENNETH ALLEN
Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.
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公开(公告)号：DE69018365D1
公开(公告)日：1995-05-11
申请号：DE69018365
申请日：1990-09-11
Applicant: IBM
Inventor： CAPPS LOUIS BENNIE , FORSTER JIMMY GRANT , PRICE WILLIAM EVERETT , RUPE ROBERT WILLIAM , UPLINGER KENNETH ALLEN
Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.
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公开(公告)号：ZA907497B
公开(公告)日：1991-06-26
申请号：ZA907497
申请日：1990-09-19
Applicant: IBM
Inventor： CAPPS LOUIS BENNIE , LOUIS BENNIE CAPPS , PRICE WILLIAM EVERETT , WILLIAM EVERETT PRICE , UPLINGER KENNETH ALLEN , KENNETH ALLEN UPLINGER , FORSTER JIMMY GRANT , JIMMY GRANT FORSTER , RUPE ROBERT WILLIAM , ROBERT WILLIAM RUPE
Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.
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公开(公告)号：AT120867T
公开(公告)日：1995-04-15
申请号：AT90309934
申请日：1990-09-11
Applicant: IBM
Inventor： CAPPS LOUIS BENNIE , FORSTER JIMMY GRANT , PRICE WILLIAM EVERETT , RUPE ROBERT WILLIAM , UPLINGER KENNETH ALLEN
Abstract: A personal computer has two memory banks (12,14) respectively connected to two parity check units (16,18) operative to detect parity errors. Upon doing so, each unit (16,18) feeds a parity error signal to a separate latch (22,24). The latches (22,24) are connected to a logic circuit (26) which is in turn connected to an interrupt controller (34) that initiates an interrupt (36) when a parity error occurs. One latch (22) is further connected to a check bit (41) of a register (40) of an I/O port (38) and the check bit (41) is set by the one latch (22). An interrupt handler reads the register and provides messages indicating which memory bank (12,14) caused the parity error.
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