公开(公告)号：CA1089112A

公开(公告)日：1980-11-04

申请号：CA180181

申请日：1973-09-04

Applicant: IBM

Inventor： CASS EUGENE E ,  ENICHEN WILLIAM A ,  HAVAS JANOS

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H05K1/04

Abstract: METHOD OF FORMING A COMPACT MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEM FOR SEMICONDUCTOR DEVICES In this method, the multi-level interconnection metallurgy system is made more compact by eliminating the need for pads normally associated with via connections between the metallurgy layers. The method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.

公开(公告)号：CA1024661A

公开(公告)日：1978-01-17

申请号：CA225413

申请日：1975-04-22

Applicant: IBM

Inventor： CASS EUGENE E

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

公开(公告)号：FR2276693A1

公开(公告)日：1976-01-23

申请号：FR7516533

申请日：1975-05-21

Applicant: IBM

Inventor： CASS EUGENE E

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/118 ,  H01L21/88 ,  H03K19/08