公开(公告)号：JPH10214784A

公开(公告)日：1998-08-11

申请号：JP977998

申请日：1998-01-21

Applicant: IBM

Inventor： ENICHEN WILLIAM A ,  ROBINSON CHRISTOPHER FREDERICK

IPC: H01J37/147 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To calibrate a system by using a first mask pattern and a calibration plate for adjusting the direction of electron beam and using a second mask pattern and a calibration plate for adjusting the magnification of electron beam. SOLUTION: A calibration plate and a mask pattern are disposed in a system 10, a linear target is swept back and forth using a linear electron beam and a signal is detected by a backscattering detector 50. When the turn of an electron beam 52 does not match that of the linear target, the backscattering signal is a pulse having a relatively wide width. When the turn matches between them, the backscattering signal is a pulse having a narrow width and a large amplitude. A calibration plate and a mask pattern are additionally disposed in a system 10. The electron beam 52 is shaped through the additional mask plate into a window pattern and an image is formed. When the magnification of the electron beam 52 is appropriate, the backscattering signal has a symmetrical shape. When the magnification is too large or too small, the backscattering signal has an asymmetrical shape.

公开(公告)号：CA1089112A

公开(公告)日：1980-11-04

申请号：CA180181

申请日：1973-09-04

Applicant: IBM

Inventor： CASS EUGENE E ,  ENICHEN WILLIAM A ,  HAVAS JANOS

IPC: H05K3/46 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H05K1/04

Abstract: METHOD OF FORMING A COMPACT MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEM FOR SEMICONDUCTOR DEVICES In this method, the multi-level interconnection metallurgy system is made more compact by eliminating the need for pads normally associated with via connections between the metallurgy layers. The method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.