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    Improvements relating to Semiconductor Devices.
    3.
    发明专利
    Improvements relating to Semiconductor Devices. 未知

    公开(公告)号：GB1151049A

    公开(公告)日：1969-05-07

    申请号：GB1667968

    申请日：1968-04-06

    Applicant: IBM

    Inventor： CASTRUCCI PAUL PHILIP

    IPC: H01L21/00 ,  H01L23/29 ,  H01L27/00 ,  H01L29/00

    Abstract: 1,151,049. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP 6 April, 1968, No. 16679/68. Heading H1K' In an integrated circuit in which conducting interconnections separated from the semiconductor body by an insulating film may tend, under certain bias conditions, to produce unwanted inversion layers, a high conductivity zone 36 of the same conductivity type as the surrounding region 32 is provided immediately beneath the interconnection 40, to interrupt the inversion channel 41. As shown the invention is applied to an integrated circuit incorporating an NPN transistor, isolated by surrounding P-type material. Another embodiment comprises two PN diodes formed by the diffusion of two spaced N-type regions into a P-type body, a P + type region being provided between the two N-type regions and beneath an insulating film and an overlying interconnection to prevent the formation of a continuous N-type inversion layer between the diodes.

    4.
    发明专利
    未知

    公开(公告)号：DE1564172B1

    公开(公告)日：1972-05-25

    申请号：DE1564172

    申请日：1966-08-22

    Applicant: IBM

    Inventor： BILOUS OREST ,  CASTRUCCI PAUL PHILIP ,  CLARK TOMMY DEAN

    IPC: H01L21/22 ,  H01L29/00 ,  H01L29/06 ,  H01L29/36 ,  H01L29/73 ,  H01L11/06

    Abstract: 1,154,856. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 8 Aug., 1966 [23 Aug., 1965], No. 35363/66. Heading H1K. The switching time of a transistor is reduced by selecting the thickness of a high resistivity epitaxial collector region between the base region and a low resistivity sub-collector region to be substantially equal to the thickness of the depletion layer. This reduces the volume of the high resistivity collector region in which minority carriers are stored, thus reducing the carrier storage time. As shown, Fig. 2, the transistor comprises an N+ type sub-collector region 10A on which is provided an N- type epitaxial collector region 12A into which are diffused base region 14A and emitter region 16A. The distance between the sub-collector region 10A and the base-collector junction 19A is selected so that at the desired operating voltage the depletion layer fills the collector region 12A. The minority carriers are stored in the region 24A but since this is in the low resistivity sub-collector region 10A they have a low storage time. A transistor is produced by epitaxially growing an N- type layer of silicon doped with phosphorus on an N+ type substrate of silicon doped with antimony. The wafer is oxidized and photo-masked and a P- type base region is produced using a "boron-capsule" technique followed by an oxidation drive-in. The oxide layer is removed from the lower face of the substrate using a blast of nitrogen-propelled alumina, and gold is vapour deposited, alloyed and diffused-in, to reduce the minority carrier lifetime. The wafer is then photomasked and phosphorus is diffused-in to form an N- type emitter region. The contact areas are exposed and a layer of aluminium is evaporated over the surface and selectively removed to produce the required electrodes which are then alloyed to the wafer. The collector region of the resulting device has a thickness of 0À1 mils, an impurity concentration of 8 x 10 14 atoms. cm -3 ., and a resistivity of 6 ohm cm.

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