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    7.
    发明专利
    未知

    公开(公告)号：DE1564218A1

    公开(公告)日：1970-01-08

    申请号：DE1564218

    申请日：1966-12-20

    Applicant: IBM

    Inventor： PHILIP PECORARO RAYMOND ,  BILOUS OREST

    IPC: H01L21/74 ,  H01L27/00 ,  H01L29/00 ,  H01L29/735 ,  H01L11/00

    Abstract: 1,159,937. Transistors. INTERNATIONAL BUSINESS MACHINES CORP. 9 Dec., 1966 [22 Dec., 1965], No. 55215/66. Heading H1K. A transistor is made by forming side by side emitter and collector zones 1000-3000 Š apart in one face of a semi-conductor layer or body by diffusion through oxide masking. Typically the two zones are of the same shape and size and their functions interchangeable, with the base contact substantially surrounding the area occupied by them. A gate electrode is preferably provided on the oxide layer over the emitter-collector gap to enable the transconductance of the device to be varied or to allow its use as an insulated gate FET with the base electrode disconnected. Base resistance may be reduced by a heavily doped zone formed by diffusion into the substrate prior to formation of the base zone proper by epitaxial deposition, the zone being extended to the base contact region by inward diffusion.

    8.
    发明专利
    未知

    公开(公告)号：DE1564172B1

    公开(公告)日：1972-05-25

    申请号：DE1564172

    申请日：1966-08-22

    Applicant: IBM

    Inventor： BILOUS OREST ,  CASTRUCCI PAUL PHILIP ,  CLARK TOMMY DEAN

    IPC: H01L21/22 ,  H01L29/00 ,  H01L29/06 ,  H01L29/36 ,  H01L29/73 ,  H01L11/06

    Abstract: 1,154,856. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 8 Aug., 1966 [23 Aug., 1965], No. 35363/66. Heading H1K. The switching time of a transistor is reduced by selecting the thickness of a high resistivity epitaxial collector region between the base region and a low resistivity sub-collector region to be substantially equal to the thickness of the depletion layer. This reduces the volume of the high resistivity collector region in which minority carriers are stored, thus reducing the carrier storage time. As shown, Fig. 2, the transistor comprises an N+ type sub-collector region 10A on which is provided an N- type epitaxial collector region 12A into which are diffused base region 14A and emitter region 16A. The distance between the sub-collector region 10A and the base-collector junction 19A is selected so that at the desired operating voltage the depletion layer fills the collector region 12A. The minority carriers are stored in the region 24A but since this is in the low resistivity sub-collector region 10A they have a low storage time. A transistor is produced by epitaxially growing an N- type layer of silicon doped with phosphorus on an N+ type substrate of silicon doped with antimony. The wafer is oxidized and photo-masked and a P- type base region is produced using a "boron-capsule" technique followed by an oxidation drive-in. The oxide layer is removed from the lower face of the substrate using a blast of nitrogen-propelled alumina, and gold is vapour deposited, alloyed and diffused-in, to reduce the minority carrier lifetime. The wafer is then photomasked and phosphorus is diffused-in to form an N- type emitter region. The contact areas are exposed and a layer of aluminium is evaporated over the surface and selectively removed to produce the required electrodes which are then alloyed to the wafer. The collector region of the resulting device has a thickness of 0À1 mils, an impurity concentration of 8 x 10 14 atoms. cm -3 ., and a resistivity of 6 ohm cm.

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