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7 records (took 0.016 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE2646343A1

    公开(公告)日：1977-06-30

    申请号：DE2646343

    申请日：1976-10-14

    Applicant: IBM

    Inventor： CHAMBERLAIN SAVVAS GEORGIOU ,  HELLER LAWRENCE GRIFFITH

    IPC: H01L31/10 ,  H01L31/113 ,  H04N3/14

    Abstract: A solid-state charge-coupled photoconductor for image scanning including a p-type substrate having a silicon dioxide layer on the surface thereof with the exception of one or more areas in which an n+ diffusion area is located. A polysilicon gate is located over the silicon dioxide layer and a second silicon dioxide layer is located over the polysilicon layer and the n+ diffusion area except for a portion where a first aluminum contact window is provided which extends through the second silicon dioxide layer to the surface of the n+ diffusion area and where a second aluminum contact window extends through the second polysilicon gate to the surface of the polysilicon gate. The photosensitivity of the device is electronically controlled due to the relatively small n+ layer which is reversed biased with respect to the larger gate area.

    CHARGE COUPLED DEVICE AND CIRCUIT ARRANGEMENT FOR ITS OPERATION
    3.
    发明专利
    CHARGE COUPLED DEVICE AND CIRCUIT ARRANGEMENT FOR ITS OPERATION 未知

    公开(公告)号：DE3377316D1

    公开(公告)日：1988-08-11

    申请号：DE3377316

    申请日：1983-03-10

    Applicant: IBM

    Inventor： CHAMBERLAIN SAVVAS GEORGIOU ,  SCHLIG EUGENE STEWART

    IPC: G11C27/04 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/768 ,  H01L29/772 ,  H01L29/78

    Abstract: The output stage of a charge coupled device comprises a series of spaced electrodes (42, 44, 46, 48) formed on an insulating layer (18) and overlying the portion of a semiconductor layer (12) lying between a pair of enhanced conductivity regions (14, 16) formed in the layer (12). The first enhanced conductivity region (14) serves as the output region of the device and the last enhanced conductivity region (16) serves as a drain region. In operation, a reset pulse is applied to the first electrode (42) of the series and phase clock pulses are applied to intermediate electrodes (44, 46) of the series in synchronism with application of the clock pulses to the electrodes (22, 28) preceding the output region (14). A set (drain) pulse is applied to the last electrode (48) of the series and also to the last electrode (24) of the electrodes preceding the output region (14). Pulsing the electrode (24) immediately preceding the output region (14) serves to increase the change in potential of that region. Pulsing of the intermediate electrodes transfers the signal charge out of the output region (14) into an induced potential well before it is transferred to the drain region (16) by the set (drain) pulse applied to the last electrode (48). This extends the upper limit of the potential change of the output region (14) and also isolates the drain region (16) to obviate "charge sloshing".

    CHARGE COUPLED DEVICE STRUCTURES AND METHODS OF USING SUCH STRUCTURE TO COMPARE TWO CHARGE PACKAGES
    4.
    发明专利
    CHARGE COUPLED DEVICE STRUCTURES AND METHODS OF USING SUCH STRUCTURE TO COMPARE TWO CHARGE PACKAGES 未知

    公开(公告)号：DE3472861D1

    公开(公告)日：1988-08-25

    申请号：DE3472861

    申请日：1984-11-14

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART ,  CHAMBERLAIN SAVVAS GEORGIOU

    IPC: G11C27/04 ,  G01R29/24 ,  G06G7/14 ,  G06G7/25 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/768 ,  H01L29/772 ,  H01L27/10

    Abstract: Two unknown charge packets are stored in adjacent potential wells of equal depth in a charge coupled device. The charge packets are then merged by changing the potential on an intermediate merge electrode to remove a potential barrier between the two wells. The potential barrier is then re-established, and a current is induced through one of the electrodes which established the two wells of equal depth, and that current is integrated as a measure of the original absolute difference between the two packets. The potential wells 24, 26 are set-up by signals VR and VG and thereafter charges Q1 Q2 introduced while signal VM on merge electrode 16 maintains the wells isolated. The charges are then merged by varying the signal VM which is then restored to its former value to isolate the wells. Various transient currents occur resulting in transistor 28 or 30 conducting charge away from capacitor 38. The potential change at output 36 represents the charge difference.

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