公开(公告)号：JP2008066721A

公开(公告)日：2008-03-21

申请号：JP2007222004

申请日：2007-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BREITWISCH MATTHEW ,  SCHROTT ALEJANDRO GABRIEL ,  CHAN HON RAMU

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide a vertical type field effect transistor array improved in performance, and a method of manufacturing the same.
SOLUTION: Each vertical part of each semiconductor pillar in a semiconductor pillar array has a line width greater than a separation distance to a neighboring semiconductor pillar. Alternatively, the array may arbitrarily includes a semiconductor pillar having a different line width within the restriction of the line width and the separation distance. A method of manufacturing the array of the semiconductor pillar uses a pillar mask layer created into a minimum dimension using photolithography, at least one of spacer layers of which is increased in an annular manner before it is used as an etching mask.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高性能的垂直型场效应晶体管阵列及其制造方法。 解决方案：半导体柱阵列中的每个半导体柱的每个垂直部分具有大于到相邻半导体柱的间隔距离的线宽。 或者，阵列可以任意地包括在线宽和间隔距离的限制内具有不同线宽的半导体柱。 制造半导体柱阵列的方法使用利用光刻法制成最小尺寸的柱掩模层，其中间隔层中的至少一个在用作蚀刻掩模之前以环形方式增加。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002083887A

公开(公告)日：2002-03-22

申请号：JP2001197828

申请日：2001-06-29

Applicant: IBM

Inventor： CHEN BOMY A ,  HARRINGTON JAY G ,  KEVIN M HALLIHAN ,  DENNIS HOINIAKKU ,  CHAN HON RAMU ,  HYUN KOO LEE ,  REBECCA D MII ,  RANKIN JED H

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for an EEPROM device, having a high performance logic (such as complementary metal-oxide semiconductor(CMOS), for example), or EEPROM device, being integrated with a nonvolatile random access memory(NVRAM). SOLUTION: The EEPROM device is provided with mutually self-matched floating gate and program gate. During programming, electronic tunneling occurs between the floating gate and the program gate.

公开(公告)号：JP2010015663A

公开(公告)日：2010-01-21

申请号：JP2008270695

申请日：2008-10-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN HON RAMU ,  RAJENDRAN BIPIN

IPC: G11C13/00 ,  G11C15/04

CPC classification number: G11C15/02 ,  G11C11/16 ,  G11C13/0004 ,  G11C15/04 ,  G11C15/046

Abstract: PROBLEM TO BE SOLVED: To provide a high density content addressable memory array using a phase change device. SOLUTION: The content addressable memory array storing stored words in memory elements is provided. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：使用相变装置提供高密度内容可寻址存储器阵列。 解决方案：提供在存储元件中存储存储字的内容可寻址存储器阵列。 每个存储器元件将至少两个互补二进制位中的一个存储为至少两个互补电阻之一。 每个存储器元件电耦合到访问设备。 内容可寻址存储器阵列的一个方面是使用偏置电路来在搜索操作期间偏置访问设备。 在搜索操作期间，接收包含位串的搜索词。 每个访问设备被偏置到搜索词中相应搜索位的互补电阻值。 如果存储在存储器元件中的位与由访问设备中的电阻表示的位互补，则指示搜索字和存储字之间的匹配。 版权所有（C）2010，JPO＆INPIT