公开(公告)号：EP1743366A4

公开(公告)日：2009-11-11

申请号：EP05746299

申请日：2005-04-21

Applicant: IBM

Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2004228074A

公开(公告)日：2004-08-12

申请号：JP2004001454

申请日：2004-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BUKOFSKY SCOTT J ,  CHEN BOMY A ,  EAMES SARA J ,  WU QIANG

IPC: H01J37/073 ,  H01J1/304 ,  H01J37/305 ,  H01J37/317 ,  H01L21/027

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/3177 ,  H01J2237/0635 ,  H01J2237/30433

Abstract: PROBLEM TO BE SOLVED: To provide an E beam system for storing calibration data and using a hyper-parallel array of electron sources assembled by an integrated circuit technology as well as a system for each beam to control individual beams, by using the calibration data. SOLUTION: The E beam system stores the calibration data by using a flash EPROM and generates one set of super-parallel beams with a scale of 1,000 beams by receiving on/off signals directed by an address system of a memory array with each electron source mounted on the memory array as a geometrical array to trace a memory array structure. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004327972A

公开(公告)日：2004-11-18

申请号：JP2004104638

申请日：2004-03-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WU QIANG ,  CHEN BOMY A

IPC: G03F7/20 ,  G01B11/00 ,  G03F9/00 ,  H01L21/027

CPC classification number: G03F9/7011 ,  G03F9/7088

Abstract: PROBLEM TO BE SOLVED: To provide equipment for positioning a wafer inside an exposure device.
SOLUTION: The equipment comprises a holder 124 constituted to hold a wafer 126 (having a plurality of positioning mark), a rough positioning device, and a fine positioning device having more accuracy than the rough positioning device. The fine positioning device has a plurality of photodetectors 122. Each photodetector is arranged in order to detect a corresponding positioning mark on the wafer. A positioning processor 120 is connected to the plurality of photodetector and holder, and controls them. The plurality of photodetectors are controlled by the positioning processor, and detect the plurality of positioning mark in parallel operation. Further, the positioning processor processes signals from the plurality of photodetector in parallel operation at a time.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于将晶片定位在曝光装置内的设备。 解决方案：设备包括：保持晶片126（具有多个定位标记）的基座124，粗略定位装置以及比粗略定位装置精度更高的精细定位装置。 精细定位装置具有多个光电检测器122.每个光电检测器被布置以便检测晶片上相应的定位标记。 定位处理器120连接到多个光电检测器和保持器，并对它们进行控制。 多个光电探测器由定位处理器控制，并行并行地检测多个定位标记。 此外，定位处理器一次处理来自多个光电检测器的信号并行操作。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214630A

公开(公告)日：2004-07-29

申请号：JP2003396388

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICHARD WISE ,  MARK C HEIKY ,  PANDA SIDDHARTHA ,  CHEN BOMY A

IPC: H05H1/46 ,  C23C16/513 ,  H01J37/32 ,  H01L21/00 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01J37/32192 ,  H01J37/32357 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To provide a system for effectively separating the reactivity of a gaseous phase reactant and the chemical reaction of a wafer surface. SOLUTION: A processing system, based on previously loaded plasma, is provided with a preliminary reaction plasma processing chamber, a power source connected to the preliminary reaction plasma processing chamber so as to drive the chamber and a wafer plasma processing chamber connected to the preliminary reaction plasma processing chamber through fluid. The preliminary reaction plasma processing chamber is constituted so as to generate reaction radicals, by subjecting to chemical reaction based on the plasma of a reaction substance. The wafer plasma processing chamber is constituted so as to allow reaction radicals to react with the seeds on the surface of a wafer arranged in the wafer plasma processing chamber. Another example includes a method for processing a wafer in a plasma environment, pre-loading a reactive gaseous flow and previously preventing the erosion of a wafer mask or an etching stop layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002083887A

公开(公告)日：2002-03-22

申请号：JP2001197828

申请日：2001-06-29

Applicant: IBM

Inventor： CHEN BOMY A ,  HARRINGTON JAY G ,  KEVIN M HALLIHAN ,  DENNIS HOINIAKKU ,  CHAN HON RAMU ,  HYUN KOO LEE ,  REBECCA D MII ,  RANKIN JED H

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for an EEPROM device, having a high performance logic (such as complementary metal-oxide semiconductor(CMOS), for example), or EEPROM device, being integrated with a nonvolatile random access memory(NVRAM). SOLUTION: The EEPROM device is provided with mutually self-matched floating gate and program gate. During programming, electronic tunneling occurs between the floating gate and the program gate.

公开(公告)号：DE602005027195D1

公开(公告)日：2011-05-12

申请号：DE602005027195

申请日：2005-04-21

Applicant: IBM

Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

公开(公告)号：WO2005104212A3

公开(公告)日：2006-07-20

申请号：PCT/US2005013601

申请日：2005-04-21

Applicant: IBM ,  WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features (16) in a layer of dielectric material (13), and forming spacers (20) on sidewalls (16s) of the features. Conductors (25) are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps (40) at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers (42, 12) above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors (25) has a bottom in contact with a low-k dielectric layer (12), a top in contact with another low-k dielectric (42), and sides in contact only with the air gaps (40). The air gaps serve to reduce the intralevel capacitance.

Abstract translation: 形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层（13）中形成多个特征（16），以及在特征的侧壁（16s）上形成间隔物（20）。 然后，导体（25）形成在特征中，通过间隔件与侧壁分离。 然后去除间隔物，在侧壁处形成气隙（40），使得导体通过气隙与侧壁分离。 在导体上方和下方的介电层（42,12）可以是介电常数小于导体之间的电介质的介电常数的低k电介质。 每个导体（25）的横截面具有与低k电介质层（12）接触的底部，与另一低k电介质（42）接触的顶部和仅与空气接触的侧面 间隙（40）。 气隙用于降低电容值。

公开(公告)号：WO0247144A3

公开(公告)日：2003-02-13

申请号：PCT/US0145195

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHEN BOMY A ,  HIRSCH ALEXANDER ,  IYER SUNDAR K ,  ROVEDO NIVO ,  WANN HSING-JEN ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/7621 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/823481

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract translation: 在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入 区。 光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。