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    4.
    发明专利
    未知

    公开(公告)号：DE3884936T2

    公开(公告)日：1994-05-05

    申请号：DE3884936

    申请日：1988-12-06

    Applicant: IBM

    Inventor： CHAN YUEN HUNG ,  NIJHUIS ROLF HENK ,  RAVADENEIRA CARLOS GUSTAVO ,  STRUK JAMES ROBERT

    IPC: G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  H03K3/288 ,  H03K5/04 ,  H03K5/13

    Abstract: An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.

    6.
    发明专利
    未知

    公开(公告)号：DE69023455T2

    公开(公告)日：1996-06-20

    申请号：DE69023455

    申请日：1990-09-21

    Applicant: IBM

    Inventor： CHAN YUEN HUNG

    IPC: G11C11/413 ,  G11C8/10 ,  G11C8/12 ,  G11C11/408 ,  G11C11/418 ,  G11C8/00

    Abstract: A word decode scheme is described, which includes word decoder circuitry for use in a static random access memory array. The invention is preferably implemented in BICMOS technology.

    7.
    发明专利
    未知

    公开(公告)号：DE69023456D1

    公开(公告)日：1995-12-14

    申请号：DE69023456

    申请日：1990-09-21

    Applicant: IBM

    Inventor： CHAN YUEN HUNG

    IPC: G11C11/413 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418 ,  G11C8/00 ,  G11C7/00

    Abstract: A bit decode scheme is described, which includes bit decoder (12 or fig. 5) and bit select circuitry (14 or fig. 6) for use in a static random access memory array. The invention is preferably implemented in BICMOS technology.

    8.
    发明专利
    未知

    公开(公告)号：DE69023455D1

    公开(公告)日：1995-12-14

    申请号：DE69023455

    申请日：1990-09-21

    Applicant: IBM

    Inventor： CHAN YUEN HUNG

    IPC: G11C11/413 ,  G11C8/10 ,  G11C8/12 ,  G11C11/408 ,  G11C11/418 ,  G11C8/00

    Abstract: A word decode scheme is described, which includes word decoder circuitry for use in a static random access memory array. The invention is preferably implemented in BICMOS technology.

    9.
    发明专利
    未知

    公开(公告)号：DE3787046T2

    公开(公告)日：1994-03-17

    申请号：DE3787046

    申请日：1987-03-27

    Applicant: IBM

    Inventor： CHAN YUEN HUNG ,  STRUK JAMES ROBERT

    IPC: G11C11/413 ,  G11C11/411 ,  G11C11/415 ,  G11C11/416 ,  G11C11/417

    Abstract: Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.

    10.
    发明专利
    未知

    公开(公告)号：DE3585811D1

    公开(公告)日：1992-05-14

    申请号：DE3585811

    申请日：1985-06-13

    Applicant: IBM

    Inventor： CHAN YUEN HUNG

    IPC: G11C11/414 ,  G11C11/415 ,  G11C11/416 ,  G11C11/40

    Abstract: The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.

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