公开(公告)号：DE3585304D1

公开(公告)日：1992-03-12

申请号：DE3585304

申请日：1985-06-13

Applicant: IBM

Inventor： CHAN YUEN HUNG ,  STRUK JAMES ROBERT

IPC: G11C11/414 ,  G11C11/34 ,  G11C11/415 ,  G11C11/416

公开(公告)号：DE3787046T2

公开(公告)日：1994-03-17

申请号：DE3787046

申请日：1987-03-27

Applicant: IBM

Inventor： CHAN YUEN HUNG ,  STRUK JAMES ROBERT

IPC: G11C11/413 ,  G11C11/411 ,  G11C11/415 ,  G11C11/416 ,  G11C11/417

Abstract: Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.

公开(公告)号：DE3884936T2

公开(公告)日：1994-05-05

申请号：DE3884936

申请日：1988-12-06

Applicant: IBM

Inventor： CHAN YUEN HUNG ,  NIJHUIS ROLF HENK ,  RAVADENEIRA CARLOS GUSTAVO ,  STRUK JAMES ROBERT

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  H03K3/288 ,  H03K5/04 ,  H03K5/13

Abstract: An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.

公开(公告)号：DE2313725A1

公开(公告)日：1973-10-11

申请号：DE2313725

申请日：1973-03-20

Applicant: IBM

Inventor： BATTISTA MARIO ALPHONSE ,  FREED LARRY ERNEST ,  HARBISON RICHARD STEPHEN ,  NESTORK WILLIAM JOHN ,  STRUK JAMES ROBERT ,  TUMAN DANIEL

IPC: H01L21/822 ,  H01L21/761 ,  H01L21/82 ,  H01L23/485 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L19/00

公开(公告)号：DE3884936D1

公开(公告)日：1993-11-18

申请号：DE3884936

申请日：1988-12-06

Applicant: IBM

Inventor： CHAN YUEN HUNG ,  NIJHUIS ROLF HENK ,  RAVADENEIRA CARLOS GUSTAVO ,  STRUK JAMES ROBERT

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  H03K3/288 ,  H03K5/04 ,  H03K5/13

Abstract: An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.

公开(公告)号：DE3787046D1

公开(公告)日：1993-09-23

申请号：DE3787046

申请日：1987-03-27

Applicant: IBM

Inventor： CHAN YUEN HUNG ,  STRUK JAMES ROBERT

IPC: G11C11/413 ,  G11C11/411 ,  G11C11/415 ,  G11C11/416 ,  G11C11/417

Abstract: Disclosed is improved bit selection circuitry for a RAM, in particular one employing CTS (Complementary Transistor Switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto bit select circuit means, each of said bit select circuit means being connected to an output of said second level decoder, a bit up-level clamp circuit connected to each of said bit select circuit means of each pair of bit lines, each of said bit select circuit means including first circuit means for increasing the speed of selection of the selected pair of bit lines, said bit up-level clamp circuit cooperating with said bit select circuit means of said selected pair of bit lines for positively limiting the upper potential level of said selected pair of bit lines, and each of said bit select circuit means including second circuit means for increasing the speed of deselection of the selected pair of bit lines.

公开(公告)号：DE2416296A1

公开(公告)日：1975-01-23

申请号：DE2416296

申请日：1974-04-04

Applicant: IBM

Inventor： STRUK JAMES ROBERT ,  WERNER ROBERT GEORGE

IPC: H03K19/088 ,  H03K19/013 ,  H03K19/08