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公开(公告)号：DE69228792T2
公开(公告)日：1999-10-07
申请号：DE69228792
申请日：1992-11-19
Applicant: IBM
Inventor： CHIDAMBARRAO DURESETI , NIJHUIS ROLF HENK , SRINIVASAN GURUMAKONDA RAMASAM , MURLEY PHILIP CLYDE , ROBBINS GORDON JAY , WALTERS TIMOTHY LAWTON
IPC: H01L23/522 , H01L21/60 , H01L21/768 , H01L23/49 , H01L23/556
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公开(公告)号：DE3884936D1
公开(公告)日：1993-11-18
申请号：DE3884936
申请日：1988-12-06
Applicant: IBM
Inventor： CHAN YUEN HUNG , NIJHUIS ROLF HENK , RAVADENEIRA CARLOS GUSTAVO , STRUK JAMES ROBERT
Abstract: An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
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公开(公告)号：DE69228792D1
公开(公告)日：1999-05-06
申请号：DE69228792
申请日：1992-11-19
Applicant: IBM
Inventor： CHIDAMBARRAO DURESETI , NIJHUIS ROLF HENK , SRINIVASAN GURUMAKONDA RAMASAM , MURLEY PHILIP CLYDE , ROBBINS GORDON JAY , WALTERS TIMOTHY LAWTON
IPC: H01L23/522 , H01L21/60 , H01L21/768 , H01L23/49 , H01L23/556
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公开(公告)号：DE3884936T2
公开(公告)日：1994-05-05
申请号：DE3884936
申请日：1988-12-06
Applicant: IBM
Inventor： CHAN YUEN HUNG , NIJHUIS ROLF HENK , RAVADENEIRA CARLOS GUSTAVO , STRUK JAMES ROBERT
Abstract: An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.
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