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公开(公告)号：US3838405A
公开(公告)日：1974-09-24
申请号：US40295673
申请日：1973-10-03
Applicant: IBM
IPC: G11C16/04 , H01L29/861 , G11C11/40
CPC classification number: H01L29/8616 , G11C16/0466
Abstract: A dense memory array in which every cross point of two insulated orthogonal sets of lines define a non-volatile memory device is described. Each device utilizes voltage and storage charge to control breakdown characteristics of a PN junction. Basically, the array comprises insulated metallic word lines orthogonal to bit line diffusions in a semiconductor body. The insulation between the word lines and the bit lines has dual charge states and can store charges. Biasing of the word and bit lines causes charges to be injected into the insulation to affect the surface field of the body and thus change the breakdown voltage of the diffusion with respect to the semiconductor body. Both the read and write operations involve voltage breakdown of the PN junction between the diffused bit line and the body. During the write operation, an avalanche breakdown of the junction is caused to occur and charge carriers are injected into the overlying insulator. The charge carriers so injected remain localized in the insulator immediately above the junction and therefore do not disturb the information on adjacent bit lines. To erase, a voltage is applied to cause the injected carriers to be driven out of the insulation into the substrate. Reading consists of sensing the breakdown voltage of the selected bit.
Abstract translation: 描述了两个绝缘正交线组的每个交叉点定义非易失性存储器件的密集存储器阵列。 每个器件利用电压和存储电荷来控制PN结的击穿特性。 基本上，该阵列包括与半导体本体中的位线扩散正交的绝缘金属字线。 字线和位线之间的绝缘具有双重充电状态并且可以存储电荷。 字和位线的偏置导致电荷注入到绝缘体中以影响身体的表面场，并因此改变扩散相对于半导体主体的击穿电压。 读和写操作都涉及扩散位线和体之间PN结的电压击穿。 在写入操作期间，导致结的雪崩击穿，并且电荷载流子被注入到上覆的绝缘体中。 如此注入的电荷载体保持在紧邻连接点上方的绝缘体中定位，因此不会干扰相邻位线上的信息。 为了擦除，施加电压以使注入的载体被驱出绝缘体进入衬底。 读取包括感测所选位的击穿电压。
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Patent Agency Ranking2.发明授权Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information 失效非挥发性半导体存储器件利用AVALANCHE注入和提取存储信息
公开(公告)号：US3797000A
公开(公告)日：1974-03-12
申请号：US3797000D
申请日：1972-12-29
Applicant: IBM
IPC: G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L11/14 , G11C11/40
CPC classification number: H01L29/7886 , G11C16/0416
Abstract: A non-volatile semiconductor storage device that can be electronically erased can be realized from a double gate field effect transistor having a first and second gates, the first gate being closer to the semiconductor body than the second gate and insulated from the body and the second gate so that it is electrically floating. When the floating gate has a thickness and is biased so that complete depletion can be achieved therein and the thickness and ionization rate product is equal to unity stored information in the form of electrons are expelled therefrom due to the effects of avalanche mechanisms.
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公开(公告)号：US3819959A
公开(公告)日：1974-06-25
申请号：US9522570
申请日：1970-12-04
Applicant: IBM
IPC: G11C19/28 , H01L29/423 , H01L29/768 , H01L11/14
CPC classification number: H01L29/42396 , G11C19/282 , G11C19/285 , G11C19/287 , H01L29/76875
Abstract: A semiconductor device which utilizes the mobility of charge in depletion regions created at the surface of a semiconductor body to transmit information and which comprises an electrode array deposited on the surface of a semiconductor body of a single type conductivity so that two out of phase electrical pulses can be applied to the electrodes comprising the array to create depletion regions of different levels in the body and thus transport a charge, injected into the semiconductor body, through the body and a sensor for measuring or detecting the transferred charges so that the described device can be used as a shift register or delay line. A plurality of the devices can be arranged to provide a simple, fast, reliable memory array.
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公开(公告)号：US3740620A
公开(公告)日：1973-06-19
申请号：US3740620D
申请日：1971-06-22
Applicant: IBM
IPC: G11C11/39 , H01L21/00 , H01L27/102 , H01L19/00
CPC classification number: H01L27/1022 , G11C11/39 , H01L21/00 , Y10S257/926
Abstract: This invention describes a homojunction transistor having a heterojunction diode formed on its emitter which can be used as a memory storage cell in a large capacity monolithic semiconductor memory array. The heterojunction diode has two stable impedance states into which it can be switched to provide the memory portion of the element while the homojunction transistor provides an isolation voltage of a specified threshold value between the forward and reverse characteristics of the heterojunction diode. The array can perform main storage, associated storage and logical functions and does not contain aberrant or ''''sneak'''' conductive paths through the memory that can provide false output signals. The cell and a method of making it is disclosed. A storage system incorporating these memory cells or elements as an array is also disclosed.
Abstract translation: 本发明描述了一种同型结晶体管，其具有形成在其发射极上的异质结二极管，其可用作大容量单片半导体存储器阵列中的存储器存储单元。
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公开(公告)号：CA925223A
公开(公告)日：1973-04-24
申请号：CA103626
申请日：1971-01-25
Applicant: IBM
IPC: H01L21/763 , H01L21/00 , H01L21/205 , H01L21/331 , H01L21/74 , H01L23/535 , H01L27/00 , H01L29/73
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