公开(公告)号：US3838405A

公开(公告)日：1974-09-24

申请号：US40295673

申请日：1973-10-03

Applicant: IBM

Inventor： ARNETT P ,  CHANG J

IPC: G11C16/04 ,  H01L29/861 ,  G11C11/40

CPC classification number: H01L29/8616 ,  G11C16/0466

Abstract: A dense memory array in which every cross point of two insulated orthogonal sets of lines define a non-volatile memory device is described. Each device utilizes voltage and storage charge to control breakdown characteristics of a PN junction. Basically, the array comprises insulated metallic word lines orthogonal to bit line diffusions in a semiconductor body. The insulation between the word lines and the bit lines has dual charge states and can store charges. Biasing of the word and bit lines causes charges to be injected into the insulation to affect the surface field of the body and thus change the breakdown voltage of the diffusion with respect to the semiconductor body. Both the read and write operations involve voltage breakdown of the PN junction between the diffused bit line and the body. During the write operation, an avalanche breakdown of the junction is caused to occur and charge carriers are injected into the overlying insulator. The charge carriers so injected remain localized in the insulator immediately above the junction and therefore do not disturb the information on adjacent bit lines. To erase, a voltage is applied to cause the injected carriers to be driven out of the insulation into the substrate. Reading consists of sensing the breakdown voltage of the selected bit.

Abstract translation: 描述了两个绝缘正交线组的每个交叉点定义非易失性存储器件的密集存储器阵列。 每个器件利用电压和存储电荷来控制PN结的击穿特性。 基本上，该阵列包括与半导体本体中的位线扩散正交的绝缘金属字线。 字线和位线之间的绝缘具有双重充电状态并且可以存储电荷。 字和位线的偏置导致电荷注入到绝缘体中以影响身体的表面场，并因此改变扩散相对于半导体主体的击穿电压。 读和写操作都涉及扩散位线和体之间PN结的电压击穿。 在写入操作期间，导致结的雪崩击穿，并且电荷载流子被注入到上覆的绝缘体中。 如此注入的电荷载体保持在紧邻连接点上方的绝缘体中定位，因此不会干扰相邻位线上的信息。 为了擦除，施加电压以使注入的载体被驱出绝缘体进入衬底。 读取包括感测所选位的击穿电压。

公开(公告)号：US3796933A

公开(公告)日：1974-03-12

申请号：US3796933D

申请日：1971-11-10

Applicant: IBM

Inventor： ARNETT P ,  HELLER L ,  STAPPER C

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/423 ,  H01L29/43 ,  H01L29/762 ,  H01L29/768 ,  H01L11/14

CPC classification number: H01L29/42396 ,  H01L29/435 ,  H01L29/76866

Abstract: A charge-coupled semiconductor device for transmitting information in the form of mobile charges through a depletion layer which comprises an electrode structure on the surface of a semiconductor body that has within it an elongated region containing an impurity gradient. When the body is biased to create a depletion under the region and packets of charges are introduced into the body near the region, the charges will under the influence of the field gradients in the depletion layer be caused to pass through the body, in a known period of time. If due to space charge broadening the charge packets slowly spread out, they may be regrouped by applying a single clock pulse to the electrode structure, which will create sharply defined potential wells under the impurity gradient. The device is particularly useful as both a delay line and as a simple, fast, reliable, memory array.

公开(公告)号：CA966229A

公开(公告)日：1975-04-15

申请号：CA156033

申请日：1972-11-08

Applicant: IBM

Inventor： ARNETT P ,  STAPPER C ,  HELLER L

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/423 ,  H01L29/43 ,  H01L29/762 ,  H01L29/768

Abstract: 1383977 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 18 Oct 1972 [10 Nov 1971] 47952/72 Heading H1K In a semi-conductor device, such as a shift register or delay line, utilizing the drift of an injected group 30 of minority-charge carriers through a depletion region 23À1 induced in a substrate 10À1 beneath an electrode structure 20À1, there is provided a graded-impurityconcentration region 17À1 of the same conductivity type as the substrate 10À1. The region 17À1 is graded in such a way that in the presence of the appropriate operating voltages on the substrate electrode 21À1, electrode structure 20À1, injecting electrode 15À1 and detecting electrode 16À1. The boundary of the depletion region 23À1 extends parallel to the device surface. In the Si shift register illustrated the electrode structure 20À1 comprises a plurality of interconnected A1 strips capacitively coupled to the ion implanted region 17À1 through a SiO2 layer 18À1. For P-type material a negative bias on the substrate electrode 21À1 induces the depletion region 23À1, the presence of the grounded strips 20À1 producing shallow potential wells 25 which are rapidly filled with injected charge-carriers. A subsequently injected charge-carrier group 30 will drift along the depletion region 23À1, but will tend to become progressively loss spatially localized due to space charge spreading. The group 30 is periodically reshaped by the application of a positive clock pulse to the electrode structure 20À1. Such a pulse temporarily deepens the potential walls 25, causing the drifting group 30 to be trapped and hence relocalized. Using this techique charge-carrier groups may be directed around carriers and in opposed directions. In a simplified embodiment constituting a delay line the electrode structure 20À1 is replaced by a single continuous electrode (20), Fig. 1 (not shown), overlying the whole length of the graded region (17À1), there being in this case no localized potential walls to reshape an injected pulse.