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1.发明授权
公开(公告)号：US3731375A
公开(公告)日：1973-05-08
申请号：US3731375D
申请日：1970-04-16
Applicant: IBM
Inventor： AGUSTA B , BARDELL P , CASTRUCCI P , HENLE R , PECORATO R
IPC: G11C11/411 , H03K3/286 , H03K3/288 , B01J17/00 , H01L1/16
CPC classification number: H03K3/286 , G11C11/4113 , H03K3/288 , Y10S438/917
Abstract: A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.
Abstract translation: 一种制造单片集成半导体结构的方法，其具有电互连的多个功能隔离的单个电池。 每个单元是从对象单元垂直，水平和对角地移位的镜像单元的对象。 多个单元提供具有由有源和无源半导体器件组成的每个存储单元的电气部件的存储器阵列。 该结构的其他重要方面包括在结构的公共部分中的地下通道连接和有源器件，其通过在结构的公共部分内的高掺杂掩埋区在相同的节点电位电互连。
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2.发明授权
公开(公告)号：US3823348A
公开(公告)日：1974-07-09
申请号：US3311970
申请日：1970-04-16
Applicant: IBM
Inventor： CASTRUCCI P , HENLE R , AGUSTA B , BARDELL P , PECORARO R
IPC: G11C11/411 , H03K3/286 , H03K3/288 , H01L5/00
CPC classification number: H03K3/286 , G11C11/4113 , H03K3/288
Abstract: A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.
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公开(公告)号：US3740620A
公开(公告)日：1973-06-19
申请号：US3740620D
申请日：1971-06-22
Applicant: IBM
IPC: G11C11/39 , H01L21/00 , H01L27/102 , H01L19/00
CPC classification number: H01L27/1022 , G11C11/39 , H01L21/00 , Y10S257/926
Abstract: This invention describes a homojunction transistor having a heterojunction diode formed on its emitter which can be used as a memory storage cell in a large capacity monolithic semiconductor memory array. The heterojunction diode has two stable impedance states into which it can be switched to provide the memory portion of the element while the homojunction transistor provides an isolation voltage of a specified threshold value between the forward and reverse characteristics of the heterojunction diode. The array can perform main storage, associated storage and logical functions and does not contain aberrant or ''''sneak'''' conductive paths through the memory that can provide false output signals. The cell and a method of making it is disclosed. A storage system incorporating these memory cells or elements as an array is also disclosed.
Abstract translation: 本发明描述了一种同型结晶体管，其具有形成在其发射极上的异质结二极管，其可用作大容量单片半导体存储器阵列中的存储器存储单元。
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4.发明授权Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information 失效非挥发性半导体存储器件利用AVALANCHE注入和提取存储信息
公开(公告)号：US3797000A
公开(公告)日：1974-03-12
申请号：US3797000D
申请日：1972-12-29
Applicant: IBM
IPC: G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L11/14 , G11C11/40
CPC classification number: H01L29/7886 , G11C16/0416
Abstract: A non-volatile semiconductor storage device that can be electronically erased can be realized from a double gate field effect transistor having a first and second gates, the first gate being closer to the semiconductor body than the second gate and insulated from the body and the second gate so that it is electrically floating. When the floating gate has a thickness and is biased so that complete depletion can be achieved therein and the thickness and ionization rate product is equal to unity stored information in the form of electrons are expelled therefrom due to the effects of avalanche mechanisms.
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公开(公告)号：US3713908A
公开(公告)日：1973-01-30
申请号：US3713908D
申请日：1970-05-15
Applicant: IBM
IPC: H01L21/761 , H01L21/8222 , H01L27/082 , H01L7/36 , H01L11/00
CPC classification number: H01L27/0821 , H01L21/761 , H01L21/8222 , Y10S148/04 , Y10S148/041
Abstract: This disclosure is primarily directed to the fabrication and construction of complementary PNP-NPN semiconductor devices in a monlithic integrated form. The devices of this disclosure use an isolation-type diffused region to form at least an emitter region thereby permitting the formation of complementary devices with both emitters having a high injection efficiency.
Abstract translation: 本公开主要涉及以单体集成形式制造和构造互补的PNP-NPN半导体器件。 本公开的器件使用隔离型扩散区域形成至少一个发射极区域，从而允许形成具有高注入效率的两个发射极的互补器件。
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Patent Agency Ranking
公开(公告)号：BE779499A
公开(公告)日：1972-06-16
申请号：BE779499
申请日：1972-02-17
Applicant: IBM
IPC: G11C19/28 , H01L29/423 , H01L29/768 , H01L
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公开(公告)号：BE780649A
公开(公告)日：1972-07-03
申请号：BE780649
申请日：1972-03-14
Applicant: IBM
Inventor： AGUSTA B , CHANG J J , FARRAR V Y DOOET P A
IPC: G11C19/28 , H01L29/00 , H01L29/423 , H01L29/768 , H01L
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