公开(公告)号：US3626390A

公开(公告)日：1971-12-07

申请号：US3626390D

申请日：1969-11-13

Applicant: IBM

Inventor： CHANG JOSEPH J ,  HO IRVING TZE ,  VOGL NORBERT G JR ,  WU BEVAN P F

IPC: G11C11/411 ,  H01L21/74 ,  H01L27/07 ,  H03K3/288 ,  G11C11/40

CPC classification number: H03K3/288 ,  G11C11/4116 ,  H01L21/74 ,  H01L27/0755 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/136

Abstract: A nondestructive read-integrated circuit memory cell consisting of a pair of cross coupled transistors. The junctions between the collectors of the transistors and the intrinsic epitaxial layer is utilized to provide isolation between the transistors. The transistors are formed by a triple-diffusion process wherein the collector region contacts a buried layer of opposite semiconductivity relative to the semiconductivity of the substrate structure. An epitaxial growth being of the same semiconductivity as the buried layer region is utilized as both a resistive material between the input and the buried layer and to form a diode gradient between the epitaxial region and the collector region of the transistors. The buried region forms a diode junction with the collector regions of the transistor to allow a bilevel operation of the memory cell.

公开(公告)号：US3865652A

公开(公告)日：1975-02-11

申请号：US40374573

申请日：1973-10-05

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J ,  JOSHI MADHUKAR L

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  H01L7/44

CPC classification number: H01L29/76866 ,  H01L21/00 ,  H01L21/823406 ,  H01L27/1057 ,  H01L29/00 ,  H01L29/1062 ,  H01L29/42396 ,  Y10S148/053 ,  Y10S148/114 ,  Y10S148/122

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

Abstract translation: 一种半导体器件，其在单个半导体本体中包含具有改善的用于存储电荷的容量的自对准场效应晶体管和电荷耦合阵列。 该器件通过在硅体表面上的二氧化硅层上沉积多晶硅和氮化硅层而形成，并且选择性地蚀刻这些层，使得合适的掺杂剂可以扩散或离子注入到下面的硅体的选定区域中以形成 在相同的半导体本体中，改进的电荷耦合阵列具有与其相关联的改进的自对准场效应晶体管。 该方法不仅导致其中在器件表面上的氧化物下面的反型层的机会大大降低的装置，而且还提供具有较薄栅极氧化物和电荷耦合阵列的自对准场效应晶体管 这增加了存储费用的能力。 这样形成的改进的阵列在操作期间还具有零间隔的耗尽区域，从而避免了在电荷耦合阵列的耗尽区域之间或内部的不期望的电中断。 因为通过使用这些薄导电层来实现零间隔，所以可以使金属相线变窄，从而在电荷转移通道中留下开口，使得该器件特别适用于成像应用。

公开(公告)号：US3621346A

公开(公告)日：1971-11-16

申请号：US3621346D

申请日：1970-01-28

Applicant: IBM

Inventor： CHANG JOSEPH J ,  VORA MADHUKAR B

IPC: H01L21/763 ,  H01L21/00 ,  H01L21/205 ,  H01L21/331 ,  H01L21/74 ,  H01L23/535 ,  H01L27/00 ,  H01L29/73 ,  H01L11/00

CPC classification number: H01L21/00 ,  H01L21/743 ,  H01L23/535 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S148/122 ,  Y10S148/145 ,  H01L2924/00

Abstract: A process wherein epitaxial silicon is grown on a substrate of single-crystal silicon with islands of silicon dioxide thereon, whereby single crystal epitaxial material is grown over the single-crystal substrate areas, but polycrystalline silicon is grown over the silicon dioxide islands. Since impurity diffusion occurs more rapidly through polycrystalline material than through single-crystalline material diffusion schemes can be obtained using the rapid diffusion pathway provided by the polycrystalline material to provide subsurface configurations which are completely enclosed by single-crystal material, for instance, a buried subcollector can be formed by growing polycrystalline silicon material horizontally, extending a narrow polycrystalline channel upward to the device surface, and subsequently diffusing impurities down through the narrow vertical polycrystalline channel into the lateral polycrystalline subcollector. Further, an electrical underpass can be formed which has a very low resistance by again using the rapid diffusion characteristics of polycrystalline silicon to grow polycrystalline silicon of the desired shape which can be rapidly diffused to provide, in comparison to background, a high conductivity path. By control of the substrate crystalline orientation, polycrystalline material can be grown which terminates because of sidewall convergence. This is desirable where it is required to terminate polycrystalline growth and begin single-crystal growth without any alteration in process conditions. The devices described are also claimed.

公开(公告)号：FR2296913A1

公开(公告)日：1976-07-30

申请号：FR7537205

申请日：1975-11-28

Applicant: IBM

Inventor： CHANG JOSEPH J ,  KENYON RICHARD A

IPC: G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/07 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

Abstract: A random access dynamic read-write FET memory system is provided with non-volatile storage of data in the event of a system power failure. The memory system includes an array of single device memory cells in which information is dynamically stored on a variable threshold non-volatile capacitor. A memory protect circuit detects system power supply failures and causes data volatively stored in the memory array to be non-volatively stored directly in the storage capacitor dielectric of each memory cell. Upon restoration of power, the non-volatively stored data is read from the array into a small auxiliary memory and the variable threshold storage capacitors are restored to their original state. Data is then returned to the memory cells in a dynamic mode.

公开(公告)号：CA976661A

公开(公告)日：1975-10-21

申请号：CA170063

申请日：1973-04-24

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J ,  JOSHI MADHUKAR L

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

公开(公告)号：CA1019441A

公开(公告)日：1977-10-18

申请号：CA186057

申请日：1973-11-16

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: 1445450 Semiconductor data storage INTERNATIONAL BUSINESS MACHINES CORP 29 Nov 1973 [29 Dec 1972] 55360/73 Heading H1K A floating gate data storage FET 10 (Fig. 1) is coupled to conventional word driver 12, bit driver 14, and bit sense amplifier 15; and comprises a semiconductor substrate 16 of, e.g. N-doped Si having opposite conductivity diffused P doped source and drain regions 17, 18 separated by channel region 19. An insulant layer 21 of SiO 2 is formed over the substrate, etched into openings for source and drain diffusion and for the channel, and an oxide layer 24 of thickness to prevent tunnelling with normal I operating voltages is reformed in the channel opening. A gate electrode 25 of semiconductor material devoid of free carriers is deposited on the oxide layer 24 and is encapsulated in insulant 26, e.g. similar to layer 24 so as to float electrically. Contacts 27, 28 are applied to source and drain diffusions 17, 18 and an overlying drive gate electrode 29 is deposited on layer 25. Drain electrode 27 is coupled over 2-piston switch 30 to bit driver 14 and sense amplifier 15 or to earth, while source electrode 28 and substrate 16 are both earthed. Drive gate 29 is connected to word driver 12. Gate 25 may consume excess charge to create conductively a channel between source 17 and drain 18 to represent logic "1"; logic "0" being denoted by its absence. For logic "1" write in, the drain electrode 27 is switched to the bit driver 14 and sense amplifier 15 and the former is driven to produce ave pulse (Fig. 2 not shown) on the drain to backbias region 18, and a + ve pulse is applied to the gate electrode 29 from the word driver 12. Avalanche breakdown between drain region 18 and substrate 16 proximate to region 19 generates high energy electrons beneath the floating gate which pass thereto through layer 24 under influence of the prevailing electric fields and are stored. The accumulated electrons induce a channel between source and drain diffusions 17, 18 and the existence or non- existence of the source denotes the presence or absence of this electron charge. Low level read pulses on drain electrode 27 and drive gate electrode 29 enable detection of stored charge by the appearance of pulses on the sense amplifier 15. Charge is removed from the floating gate 25 to eliminate the induced channel and erase the storage by setting switch 30 to earth and negatively pulsing drive gate 29 from the word driver 12 so as to deplete the floating gate by avalanche breakedown into region 19. Plural short pulses may be used for erasure.

公开(公告)号：GB1264260A

公开(公告)日：1972-02-16

申请号：GB5236970

申请日：1970-11-04

Applicant: IBM

Inventor： CHANG JOSEPH J ,  HO IRVING TZE ,  VOGL NORBERT G JR ,  WU BEVAN P F

IPC: G11C11/411 ,  H01L21/74 ,  H01L27/07 ,  H03K3/288

Abstract: 1,264,260. Integrated semi-conductor circuits. INTERNATIONAL BUSINESS MACHINES CORP. 4 Nov., 1970 [13 Nov., 1969], No. 52369/70. Heading H1K. A monolithic integrated circuit non-destructive memory comprises an array of bi-level operational pairs of transistors each with grounded base and collector-base cross connection. Read-in is by-switching the transistors of a pair from non-conducting-conducting to conducting-non-conducting conditions respectively, and read-out by applying P.D.'s across the collector-emitter circuit and to the emitter,. and then sensing current in the conducting transistor Fig. 1, Fig. 4 (not shown); the diodes and resistors R1 1 , R2 1 , R3 1 being connected in series with each transistor and with address input Y 0 . A single chip memory cell (Figs. 2, 3) comprises transistors 10, 12 surrounded by a diffused isolation region 20, and an epitaxial region 28 of the same conductivity type as the buried cathode 24 of diodes 13, which operates to provide resistances in series with diode cathodes and input region 30 in delta network R 1 , R 2 , R 3 . This is reducible in known manner to a Y equivalent for resistors R 1 1 , R 2 1 , and R 3 1 as functions of the values R1, R2, R3, which are controllable by doping the epitaxial region 28 and by the size and position of diffused control region 26. Since region 28 has differing conductivity type from collector region 38 of the transistors, the latter forms a diode in the region 24 across interface 40, and also with region 28 across the collector interface, whereby diodes 13 exist at each input and a further diode (not shown) is provided between the collectors isolating the adjacent transistors of the memory cell; avoiding the necessity for individual isolation rings. The buried island cathode 24 removes virtual collector-substrate capacitance to the cathode of diode 13, so as to reduce transient switching error. Structurally (Fig. 3) a silicon body 22 of P-conductivity is formed with holes for cathodes of diodes 13, indicated by buried island region 24 of N-type conductivity. A further hole is simultaneously formed between the isolation region and each transistor as a controlled diffusion region 26 of N-type-conductivity; the buried island and control region being formed by diffusion. Thereafter an epitaxial region 28 doped. N-conductivity is grown over the substrate, operating as a resistance path connected to cathode 24 of diodes 13 formed between island 40 and collectors 38 of the transistors; each cell having two transistors formed over two buried island regions 24. Isolation ring 20 is then diffused about the cell, and the transistors are formed by triple diffusion of a P-type collector region, a N-type base region, and a P + -type emitter region. N-type input region 30 is equidistantly diffused relative to both transistors, and ohmic contacts are formed on the semi-conductor regions; contact 31 being Y 0 input, contact 32 being inter-transistor collectorbase connection, contact 34 being dual emitter connection for X line and ground Y 1 , and contact 36 being the common N base connection. An underpass P + region (not shown) may provide the collector-base connection, and negative potential (not shown) may be imposed on the P + region 20. Either PNP or NPN transistors may be employed, and the use of an epitaxial layer as resistance between active elements and to provide inter-element isolation is applicable to any integrated circuit.

公开(公告)号：CA864743A

公开(公告)日：1971-02-23

申请号：CA864743D

Applicant: IBM

Inventor： VORA MADHUKAR B ,  CHANG JOSEPH J

公开(公告)号：CA1038496A

公开(公告)日：1978-09-12

申请号：CA239394

申请日：1975-11-12

Applicant: IBM

Inventor： CHANG JOSEPH J ,  KENYON RICHARD A

IPC: G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/07 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

Abstract: DYNAMIC MEMORY WITH NON-VOLATILE BACK-UP MODE A random access dynamic read-write FET memory system is provided with non-volatile storage of data in the event of a system power failure. The memory system includes an array of single device memory cells in which information is dynamically stored on a variable threshold nonvolatile capacitor. A memory protect circuit detects system power supply failures and causes data volatively stored directly in the storage capacitor dielectric of each memory cell. Upon restoration of power, the non-volatively stored data is read from the array into a small auxiliary memory and the variable threshold storage capacitors are restored to their original state. Data is then returned to the memory cells in a dynamic mode.

公开(公告)号：CA964772A

公开(公告)日：1975-03-18

申请号：CA144639

申请日：1972-06-14

Applicant: IBM

Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J

IPC: G11C11/39 ,  H01L21/00 ,  H01L27/102

Abstract: This invention describes a homojunction transistor having a heterojunction diode formed on its emitter which can be used as a memory storage cell in a large capacity monolithic semiconductor memory array.