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    Method of forming self-aligned field effect transistor and charge-coupled device
    3.
    发明授权
    Method of forming self-aligned field effect transistor and charge-coupled device 失效
    形成自对准场效应晶体管和电荷耦合器件的方法

    公开(公告)号：US3865652A

    公开(公告)日：1975-02-11

    申请号：US40374573

    申请日：1973-10-05

    Applicant: IBM

    Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J ,  JOSHI MADHUKAR L

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  H01L7/44

    CPC classification number: H01L29/76866 ,  H01L21/00 ,  H01L21/823406 ,  H01L27/1057 ,  H01L29/00 ,  H01L29/1062 ,  H01L29/42396 ,  Y10S148/053 ,  Y10S148/114 ,  Y10S148/122

    Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

    Abstract translation: 一种半导体器件，其在单个半导体本体中包含具有改善的用于存储电荷的容量的自对准场效应晶体管和电荷耦合阵列。 该器件通过在硅体表面上的二氧化硅层上沉积多晶硅和氮化硅层而形成，并且选择性地蚀刻这些层，使得合适的掺杂剂可以扩散或离子注入到下面的硅体的选定区域中以形成 在相同的半导体本体中，改进的电荷耦合阵列具有与其相关联的改进的自对准场效应晶体管。 该方法不仅导致其中在器件表面上的氧化物下面的反型层的机会大大降低的装置，而且还提供具有较薄栅极氧化物和电荷耦合阵列的自对准场效应晶体管 这增加了存储费用的能力。 这样形成的改进的阵列在操作期间还具有零间隔的耗尽区域，从而避免了在电荷耦合阵列的耗尽区域之间或内部的不期望的电中断。 因为通过使用这些薄导电层来实现零间隔，所以可以使金属相线变窄，从而在电荷转移通道中留下开口，使得该器件特别适用于成像应用。

    SELF-ALIGNED FIELD EFFECT TRANSISTOR AND CHARGE-COUPLED DEVICE
    4.
    发明专利
    SELF-ALIGNED FIELD EFFECT TRANSISTOR AND CHARGE-COUPLED DEVICE 未知

    公开(公告)号：CA976661A

    公开(公告)日：1975-10-21

    申请号：CA170063

    申请日：1973-04-24

    Applicant: IBM

    Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J ,  JOSHI MADHUKAR L

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768

    Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

    CAPACITOR MEMORY WITH AN AMPLIFIED CELL SIGNAL
    6.
    发明专利
    CAPACITOR MEMORY WITH AN AMPLIFIED CELL SIGNAL 未知

    公开(公告)号：CA1114504A

    公开(公告)日：1981-12-15

    申请号：CA300415

    申请日：1978-04-04

    Applicant: IBM

    Inventor： JOSHI MADHUKAR L ,  PRICER WILBUR D

    IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/24

    Abstract: CAPACITOR MEMORY WITH AN AMPLIFIED CELL SIGNAL A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

    7.
    发明专利
    未知

    公开(公告)号：FR2316740A1

    公开(公告)日：1977-01-28

    申请号：FR7615011

    申请日：1976-05-13

    Applicant: IBM

    Inventor： BHATTACHARYYA ARUP ,  JOSHI MADHUKAR L ,  KROLL CHARLES T ,  SILVERMAN RONALD

    IPC: H01L27/112 ,  G11C17/00 ,  G11C17/08 ,  H01L21/3105 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/04 ,  H01L21/72 ,  G11C11/40

    Abstract: Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.

    8.
    发明专利
    未知

    公开(公告)号：DD141082A5

    公开(公告)日：1980-04-09

    申请号：DD20634778

    申请日：1978-06-28

    Applicant: IBM

    Inventor： JOSHI MADHUKAR L ,  PRICER WILBUR D

    IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/40

    Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

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