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    MEMORY CELL
    1.
    发明专利
    MEMORY CELL 未知

    公开(公告)号：DE3279630D1

    公开(公告)日：1989-05-24

    申请号：DE3279630

    申请日：1982-06-29

    Applicant: IBM

    Inventor： CHAO HU HERBERT ,  DIMARIA DONELLI JOSEPH

    IPC: H01L27/112 ,  G11C14/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

    Abstract: A non-volatile dynamic semiconductor memory cell comprises a one device dynamic volatile memory circuit associated with bit line (BL) and having a switching device (FET 14) and a storage capacitor (Cs); and a non-volatile floating gate device disposed between the storage node (10) and the switching device. The non-volatile floating gate device has a floating gate (FG), a floating gate FET (3), a control gate (P) and a voltage divider (16) having first and second serially-connected capacitors (C1, C2), with the floating gate being disposed at the common point between the first and second capacitors. One of the capacitors (C1) includes a dual charge or electron injector structure and the capacitance of this capacitor has a value substantially less than that of the other capacitor (C2).

    2.
    发明专利
    未知

    公开(公告)号：DE69031527D1

    公开(公告)日：1997-11-06

    申请号：DE69031527

    申请日：1990-03-20

    Applicant: IBM

    Inventor： CHAO HU HERBERT ,  CHANG JUNG-HERNG

    IPC: G06F11/10 ,  G06F12/08

    Abstract: A scheme for the implementation of single error correction, double error detection function is provided for cache memories wherein the normal cache access time is not affected by the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a single error is detected, a cycle is inserted by the control circuitry of the cache chip. At the same time, the clocks for the CPU are held high until released by the cache chip on the next cycle. Error correction on multi-byte data is performed using, for example, the 72/64 Hamming code. The technique requires a 2-port cache array (one write port, and one read port). However, the density of a true 2-port array is too low; therefore, the technique is implemented with a 1-port array using a time multiplexing technique, providing an effective 2-port array but with the density of a single port array.

    3.
    发明专利
    未知

    公开(公告)号：DE69031527T2

    公开(公告)日：1998-03-26

    申请号：DE69031527

    申请日：1990-03-20

    Applicant: IBM

    Inventor： CHAO HU HERBERT ,  CHANG JUNG-HERNG

    IPC: G06F11/10 ,  G06F12/08

    Abstract: A scheme for the implementation of single error correction, double error detection function is provided for cache memories wherein the normal cache access time is not affected by the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a single error is detected, a cycle is inserted by the control circuitry of the cache chip. At the same time, the clocks for the CPU are held high until released by the cache chip on the next cycle. Error correction on multi-byte data is performed using, for example, the 72/64 Hamming code. The technique requires a 2-port cache array (one write port, and one read port). However, the density of a true 2-port array is too low; therefore, the technique is implemented with a 1-port array using a time multiplexing technique, providing an effective 2-port array but with the density of a single port array.

    5.
    发明专利
    未知

    公开(公告)号：DE3583004D1

    公开(公告)日：1991-07-04

    申请号：DE3583004

    申请日：1985-11-05

    Applicant: IBM

    Inventor： CHAO HU HERBERT ,  LU NICKY CHAU-CHUN

    IPC: G11C11/407 ,  G11C8/08 ,  G11C8/00

    Abstract: @ A voltage boosting circuit combination for semiconductor memory word-lines having a charge/discharge circuit including a first pair of MOSFET's (20, 24) and connected to a first clock signal ΦA. An output lead (12) is connected from the charge/discharge circuit to a word-line of a semiconductor memory. The first clock signal ΦA thereon is connected to the charge/discharge circuit for actuating the MOSFET's to produce a voltage change on the output lead from a first voltage level to a second voltage level. The circuit combination also includes a threshold voltage circuit having a second pair of MOSFET's (34), which is connected to a second clock signal ΦC for controlling the voltage level in the threshold voltage circuit. A lead (19) is provided connecting the threshold voltage circuit to the charge/discharge circuit. The circuit combination further includes an output signal boosting circuit having a third pair of MOSFET's (30, 32) which is connected to a third clock signal OD for actuating the MOSFET's to produce a voltage boosting signal. A capacitor device (28) is provided for connecting the boosting circuit to the output lead (12) for applying the voltage boosting signal from the voltage boosting circuit to the output lead for enhancing the voltage level change on the output lead to the first voltage level from the second voltage level.

    6.
    发明专利
    未知

    公开(公告)号：DE3675423D1

    公开(公告)日：1990-12-13

    申请号：DE3675423

    申请日：1986-04-08

    Applicant: IBM

    Inventor： CHAO HU HERBERT ,  LU NICKY CHAU-CHUN

    IPC: G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C8/00 ,  G11C11/401

    Abstract: A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters are used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock.A high performance decoder circuit is provided in combination with the aforesaid SMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.In order to boost the word-line below 0 V, a negative substrate bias is provided which avoids the junction forward-biasing due to voltage undershoot below 0 V at NMOS source or drain, thus simplifying the design and speeding up the word-line clock pull-down when compared to the word-line boost clock circuit without using the substrate bias.An embodiment is shown in the drawings in which block 11 is a NOR gate which sums the two clock signals ø B and ø AS . Blocks 13 and 15 include a chain of delay circuits. Block 17 is a delay circuit for clock signal ø B . Blocks 19 and 21 also include chains of delay circuits. Block 23 functions as a gate wherein clock signal ø C is stored at a device Q 24 and is gated to delay block 19 when a signal is applied to device Q23.Block 25 is a NOR circuit for delayed signal ø c from block 15 and delayed signal ø D from block 21. Block 27 is a NAND circuit for the output of NOR circuit 25 and an external boost output signal (from block 33). Block 29 is an internal boost circuit for node 22 to control the device Q,. Block 31 is a clock driver means and block 22 is an external boosting means. Block 35 performs a NAND function for the delayed ø D signal from block 21 and the delayed ø B signal from block 17.

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