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公开(公告)号：DE69519886T2
公开(公告)日：2001-06-21
申请号：DE69519886
申请日：1995-03-14
Applicant: IBM
Inventor： CHENEY DENNIS PHILLIP , CONZOLA VINCENT CHARLES , NGAI CHUCK HONG , PFEIFFER RICHARD THOMAS
Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. The decoder system includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.
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Patent Agency Ranking
公开(公告)号：DE69125815T2
公开(公告)日：1997-10-23
申请号：DE69125815
申请日：1991-12-10
Applicant: IBM
Inventor： CHENEY DENNIS PHILLIP , YAGLEY ROBERT JOSEPH , WOLSKI MARK JAMES , PETRUSKI ANDREW EDWARD , BOSTON JOSEPHINE ANN
Abstract: A system and method for striping data to multiple storage devices (106) is disclosed. One embodiment of the present invention sequentially gates data to a plurality of buffers (304), wherein only those buffers (304) corresponding to storage devices (106) in use are induced to gate in data. The data is then sent to the storage devices (106) in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.
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公开(公告)号：DE69125815D1
公开(公告)日：1997-05-28
申请号：DE69125815
申请日：1991-12-10
Applicant: IBM
Inventor： CHENEY DENNIS PHILLIP , YAGLEY ROBERT JOSEPH , WOLSKI MARK JAMES , PETRUSKI ANDREW EDWARD , BOSTON JOSEPHINE ANN
Abstract: A system and method for striping data to multiple storage devices (106) is disclosed. One embodiment of the present invention sequentially gates data to a plurality of buffers (304), wherein only those buffers (304) corresponding to storage devices (106) in use are induced to gate in data. The data is then sent to the storage devices (106) in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.
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公开(公告)号：DE69736620T2
公开(公告)日：2007-09-06
申请号：DE69736620
申请日：1997-02-21
Applicant: IBM
Inventor： CHENEY DENNIS PHILLIP , HRUSECKY DAVID ALLEN , STOJANCIC MIHAILO M
IPC: H04N5/92 , G06T9/00 , G09G1/16 , G09G5/39 , H03M7/36 , H04N5/44 , H04N7/32 , H04N21/4143 , H04N21/4402 , H04N21/443
Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals with accurate expansion for various aspect ratios.
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公开(公告)号：DE69736620D1
公开(公告)日：2006-10-19
申请号：DE69736620
申请日：1997-02-21
Applicant: IBM
Inventor： CHENEY DENNIS PHILLIP , HRUSECKY DAVID ALLEN , STOJANCIC MIHAILO M
IPC: H04N5/92 , G06T9/00 , G09G1/16 , G09G5/39 , H03M7/36 , H04N5/44 , H04N7/32 , H04N21/4143 , H04N21/4402 , H04N21/443
Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals with accurate expansion for various aspect ratios.
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公开(公告)号：DE69519886D1
公开(公告)日：2001-02-22
申请号：DE69519886
申请日：1995-03-14
Applicant: IBM
Inventor： CHENEY DENNIS PHILLIP , CONZOLA VINCENT CHARLES , NGAI CHUCK HONG , PFEIFFER RICHARD THOMAS
Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. The decoder system includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.
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