公开(公告)号：DE69519886T2

公开(公告)日：2001-06-21

申请号：DE69519886

申请日：1995-03-14

Applicant: IBM

Inventor： CHENEY DENNIS PHILLIP ,  CONZOLA VINCENT CHARLES ,  NGAI CHUCK HONG ,  PFEIFFER RICHARD THOMAS

IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. The decoder system includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

公开(公告)号：DE69519886D1

公开(公告)日：2001-02-22

申请号：DE69519886

申请日：1995-03-14

Applicant: IBM

Inventor： CHENEY DENNIS PHILLIP ,  CONZOLA VINCENT CHARLES ,  NGAI CHUCK HONG ,  PFEIFFER RICHARD THOMAS

IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. The decoder system includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM. The decoder has a decoder processor that includes a Variable Length Code Decoder for receiving encoded data, a (2,3,3) parallel counter based Inverse Quantizer for dequantizing the decoded data, an Inverse Discrete Cosine Transform Decoder for transforming the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures, a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM, a Display Unit to output motion compensated pictures from the RAM, and a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.