公开(公告)号：DE68922819T2

公开(公告)日：1995-12-14

申请号：DE68922819

申请日：1989-08-02

Applicant: IBM

Inventor： CHIN DAEJE ,  DHONG SANG H

IPC: H01L27/10 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/82 ,  H01L21/76

Abstract: This invention relates generally to ultra dense dynamic random access semiconductor memory arrays. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates (6) of the adjacent transfer devices of the one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate (8, 11, 12) effectively acts as a counterelectrode surrounding the insulated drain regions (5) of each of the one device memory cells. A pair of gates (6) are disposed in insulating conduits (15) which run perpendicular to the rows of memory cells. Each gate (6) in a conduit is disposed in insulated spaced relationship with a memory cell channel region (4) which, in response to signals on the gate turns on a column of channel regions (4) so as to permit the entry of charge into a selected storage region when a bitline (16) associated with a particular cell (2) is energized. The resulting array shows rows of pairs of memory cells (2) wherein each cell of a pair is spaced from the other by a portion (12) of the substrate acting as a counterelectrode and each of the pairs of memory cells is similarly separated from an adjacent pair by regions (11) of conductive material acting as a counterelectrode.

公开(公告)号：DE3786434T2

公开(公告)日：1994-01-20

申请号：DE3786434

申请日：1987-09-08

Applicant: IBM

Inventor： CHIN DAEJE ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

Abstract: A memory device, in particular, a dynamic random access memory (DRAM), is comprised of a first (12) and a second (14) input/output (I/O) bus, a first (20) and a second (28) I/O sense amplifier, and a first (24) and a second (30) I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal (32) for enabling the operation of the I/O busses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per Column Address Strobe (CAS) cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O busses are alternately enabled, one being enabled when CAS (40) is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

公开(公告)号：DE3786434D1

公开(公告)日：1993-08-12

申请号：DE3786434

申请日：1987-09-08

Applicant: IBM

Inventor： CHIN DAEJE ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

Abstract: A memory device, in particular, a dynamic random access memory (DRAM), is comprised of a first (12) and a second (14) input/output (I/O) bus, a first (20) and a second (28) I/O sense amplifier, and a first (24) and a second (30) I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal (32) for enabling the operation of the I/O busses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per Column Address Strobe (CAS) cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O busses are alternately enabled, one being enabled when CAS (40) is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

公开(公告)号：DE68922819D1

公开(公告)日：1995-06-29

申请号：DE68922819

申请日：1989-08-02

Applicant: IBM

Inventor： CHIN DAEJE ,  DHONG SANG H

IPC: H01L27/10 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/82 ,  H01L21/76

Abstract: This invention relates generally to ultra dense dynamic random access semiconductor memory arrays. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates (6) of the adjacent transfer devices of the one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate (8, 11, 12) effectively acts as a counterelectrode surrounding the insulated drain regions (5) of each of the one device memory cells. A pair of gates (6) are disposed in insulating conduits (15) which run perpendicular to the rows of memory cells. Each gate (6) in a conduit is disposed in insulated spaced relationship with a memory cell channel region (4) which, in response to signals on the gate turns on a column of channel regions (4) so as to permit the entry of charge into a selected storage region when a bitline (16) associated with a particular cell (2) is energized. The resulting array shows rows of pairs of memory cells (2) wherein each cell of a pair is spaced from the other by a portion (12) of the substrate acting as a counterelectrode and each of the pairs of memory cells is similarly separated from an adjacent pair by regions (11) of conductive material acting as a counterelectrode.