公开(公告)号：JPH0644571B2

公开(公告)日：1994-06-08

申请号：JP29703390

申请日：1990-11-01

Applicant: IBM

Inventor： TEECHIYAN CHIEN ,  CHINNTE KENTO CHIYUAN ,  GUANNPIYON RI ,  TAKU HAN NIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

公开(公告)号：JPH04130823A

公开(公告)日：1992-05-01

申请号：JP41579590

申请日：1990-12-28

Applicant: IBM

Inventor： CHINNTE KENTO CHIYUAN ,  HIYUN JIYON SHIN

IPC: H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H03K17/567 ,  H03K19/01 ,  H03K19/013 ,  H03K19/086

Abstract: PURPOSE: To improve the switching speed of a whole ECL device by connecting a junction field effect transistor(FET) with a pull-up circuit in one line and adjusting the depression area of the standard gate of the transistor(FET) so as to decrease or increase the conductivity between the source and drain of the FET. CONSTITUTION: A back gate 14 is provided so as to provide additional conducting path adjustment for further controlling the overall impedance of the ECL device during switching operations between the source 9 and drain 13 of a junction FET. The back gate 14 of the junction FET is connected to a preceding logical stage 25 and switched by gate connection. While the output logical state is switched from logic '1' to logic '2', the impedance of a pull- down device 30 is dropped in the initial stage for modulating the back gate 14 connected to a depression area limited by a standard gate and an N-type well 8. The instantaneous drop of the impedance increases the current flowing to the drain from the source and quickly discharges the potential at a load connecting section.

公开(公告)号：JPH03178133A

公开(公告)日：1991-08-02

申请号：JP29703390

申请日：1990-11-01

Applicant: IBM

Inventor： TEECHIYAN CHIEN ,  CHINNTE KENTO CHIYUAN ,  GUANNPIYON RI ,  TAKU HAN NIN

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

Abstract: PURPOSE: To prevent the punch-through of an edge or the breakdown from occurring by demarcating the base and emitter regions of a transistor, enabling one portion of a junction to be in parallel with at least a boundary surface, and providing a mesa-shaped p-n junction that ends at an insulating layer and where a polycrystalline region is electrically connected to the emitter region. CONSTITUTION: A p-n junction 5 of base-collector is formed at the boundary between a base 2 and a collector 4, and an oxide layer 6 partially covers the polycrystalline region of an extrinsic base 3, excluding a part that is directly connected to an intrinsic base 2. A silicon nitride layer 7 covers the oxide layer 6 and includes an extension part 8, and the edge part of the extension part demarcates the width of a base-emitter p-n junction 9. The p-n junction 9 is of mesa shape, the side part ends at the extension part 8 at one edge, and ends at the edge part of the flat part of the p-n junction 9 at the other edge, thus essentially eliminating punch-through or breakdown of the edge.