公开(公告)号：JP2007200523A

公开(公告)日：2007-08-09

申请号：JP2006346800

申请日：2006-12-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEE MICHAEL JU HYEOK ,  KLIM PETER J ,  JOSE A PAREDES ,  CHU SAM GAT-SHANG

IPC: G11C11/413 ,  G11C11/407 ,  G11C11/41

CPC classification number: G11C8/10

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for performing selective row energization based on write data by using a selective row energization system.
SOLUTION: The system includes: a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detection circuit 110 which responds to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detection register 112 having M uniform-detection latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated row; and an M-bit row driver device 116 which responds to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过使用选择行通电系统来基于写入数据执行选择性行激励的系统和方法。 解决方案：该系统包括：具有M行104和N列106的存储阵列102; N位数据字寄存器108; 均匀检测电路110，响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联并且存储用于存储在相关行中的数据字的统一字数据位; 以及M位行驱动器设备116，其响应M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003022293A

公开(公告)日：2003-01-24

申请号：JP2002075699

申请日：2002-03-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CHU SAM GAT-SHANG ,  CLABES JOACHIM GERHARD ,  GOULET MICHAEL NORMAND ,  ROSSER THOMAS EDWARD ,  WARNOCK JAMES DOUGLAS

IPC: G06F1/10 ,  G06F1/12 ,  G06F17/50 ,  H03K3/037

CPC classification number: G06F17/505

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for reducing the power consumption of a clocked circuit including a plurality of latches. SOLUTION: A first latch which has more than a prescribed slack is detected within the plurality of latches. Then, the possibility of substituting an available second latch (requiring less power to operate) is determined subject to the constraint that the slack after substitution should still be positive although it may be less than the prescribed number above. When such a possibility is determined to exist, the first latch is replaced with the available second latch.

Abstract translation: 要解决的问题：提供一种降低包括多个锁存器的时钟电路的功耗的方法和装置。 解决方案：在多个锁存器内检测到具有多于规定松弛度的第一锁存器。 然后，取决于可用的第二个锁存器（需要更少的功率来操作）的可能性被确定为受限制，即替换后的松弛仍然是正的，尽管它可能小于上述规定的数量。 当确定存在这种可能性时，第一锁存器被可用的第二锁存器替换。

公开(公告)号：JPH11261406A

公开(公告)日：1999-09-24

申请号：JP1261699

申请日：1999-01-21

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KODALI VISWESWARA RAO ,  LEE MICHAEL JU HYEOK

IPC: H03K19/003 ,  G06F11/00 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To protect a logical condition potential level in a logical circuit despite a collision of an alpha-particle. SOLUTION: A logical circuit senses inappropriate or earlier switching start by a collision of an alpha-particle or the like and operates so as to hold an appropriate logical level in the logical circuit. In an execution configuration, an internal node 603 of an upper part circuit in a dual rail logical circuit is connected to a gate terminal of a crossover connection PFET element 623 in a lower part circuit. This crossover connection PFET element 623 senses switch operation started at an inappropriate time in the upper part circuit, again operates a holding PFET in the upper part circuit, and can operate so that it reestablishes an appropriate logical potential level in the upper part circuit.

公开(公告)号：DE602005015336D1

公开(公告)日：2009-08-20

申请号：DE602005015336

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/22

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

公开(公告)号：CA2577272A1

公开(公告)日：2006-02-23

申请号：CA2577272

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/22

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

公开(公告)号：AT436073T

公开(公告)日：2009-07-15

申请号：AT05779156

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/22

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.