公开(公告)号：JP2008146812A

公开(公告)日：2008-06-26

申请号：JP2007291987

申请日：2007-11-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BAO G TRUONG ,  LEE MICHAEL JU HYEOK

IPC: G11C11/41

CPC classification number: G11C7/22 ,  G11C11/413 ,  G11C2207/2227

Abstract: PROBLEM TO BE SOLVED: To provide a mechanism for reducing the amount of power consumed by an SRAM array during accessing of the SRAM array.
SOLUTION: A logic means is provided for determining the polarity of an incoming row written to the SRAM array. A logical means is further provided for storing a polarity value in an additional SRAM cell per row of the SRAM array. A logical means is also provided for reading an inverted value of the SRAM cells of a row in the SRAM cell array if the row contains more 0's than 1's, as determined based on the polarity value stored in the additional SRAM cell per row. A logical means is further provided for signaling to a down stream logical means whether the data read from the SRAM cells in the row represents the true data values or their complement, as determined based on the polarity value stored in the additional SRAM cell per row.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在SRAM阵列访问期间减少由SRAM阵列消耗的功率量的机构。 解决方案：提供一种用于确定写入SRAM阵列的输入行的极性的逻辑装置。 还提供了一种逻辑装置，用于将SRAM极性值存储在SRAM阵列每行的附加SRAM单元中。 如果根据存储在每行的附加SRAM单元中的极性值确定的行，如果行包含多于0的逻辑单元，则还提供用于读取SRAM单元阵列中的行的SRAM单元的反相值的逻辑装置。 进一步提供逻辑手段，用于向下游逻辑装置发信号，根据存储在每行附加SRAM单元中的极性值确定，从行中的SRAM单元读取的数据是否表示真实数据值或其补码。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007200523A

公开(公告)日：2007-08-09

申请号：JP2006346800

申请日：2006-12-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEE MICHAEL JU HYEOK ,  KLIM PETER J ,  JOSE A PAREDES ,  CHU SAM GAT-SHANG

IPC: G11C11/413 ,  G11C11/407 ,  G11C11/41

CPC classification number: G11C8/10

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for performing selective row energization based on write data by using a selective row energization system.
SOLUTION: The system includes: a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detection circuit 110 which responds to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detection register 112 having M uniform-detection latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated row; and an M-bit row driver device 116 which responds to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过使用选择行通电系统来基于写入数据执行选择性行激励的系统和方法。 解决方案：该系统包括：具有M行104和N列106的存储阵列102; N位数据字寄存器108; 均匀检测电路110，响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联并且存储用于存储在相关行中的数据字的统一字数据位; 以及M位行驱动器设备116，其响应M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH11261406A

公开(公告)日：1999-09-24

申请号：JP1261699

申请日：1999-01-21

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KODALI VISWESWARA RAO ,  LEE MICHAEL JU HYEOK

IPC: H03K19/003 ,  G06F11/00 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To protect a logical condition potential level in a logical circuit despite a collision of an alpha-particle. SOLUTION: A logical circuit senses inappropriate or earlier switching start by a collision of an alpha-particle or the like and operates so as to hold an appropriate logical level in the logical circuit. In an execution configuration, an internal node 603 of an upper part circuit in a dual rail logical circuit is connected to a gate terminal of a crossover connection PFET element 623 in a lower part circuit. This crossover connection PFET element 623 senses switch operation started at an inappropriate time in the upper part circuit, again operates a holding PFET in the upper part circuit, and can operate so that it reestablishes an appropriate logical potential level in the upper part circuit.

公开(公告)号：DE602005015336D1

公开(公告)日：2009-08-20

申请号：DE602005015336

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/22

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

公开(公告)号：AT436073T

公开(公告)日：2009-07-15

申请号：AT05779156

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/22

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

公开(公告)号：MX2007002013A

公开(公告)日：2007-03-28

申请号：MX2007002013

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM-GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/00

Abstract: Un aparato y metodo de archivo de registro que incorpora bloqueo de lectura-despues-de escritura utilizando celdas de deteccion proporciona tiempos de acceso de lectura mejorados en archivos de registro de alto rendimiento. Una o mas celdas de deteccion identicas a las celdas del archivo de registro y ubicadas en el arreglo de archivos de registro se utilizan para controlar la operacion de lectura en el archivo de registro al configurar las celdas de deteccion ya sea aun valor alterno en cada escritura o cambio a un valor particular despues de una escritura y luego detectar cuando la escritura se ha completado al detectar el cambio de estado de una celda de deteccion activa. La deteccion del cambio de estado puede emplearse para retrasar el borde delantero de un estrobo del lectura o puede utilizarse en la logica de control de acceso para retrasar la generacion de un siguiente estrobo de lectura. El archivo de registro de esta manera proporciona un diseno ajustable en escala que no tiene que afinarse para cada aplicacion y que da seguimiento localiza sobre la variacion de sesgo de reloj y voltaje.

公开(公告)号：CA2577272A1

公开(公告)日：2006-02-23

申请号：CA2577272

申请日：2005-08-19

Applicant: IBM

Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

IPC: G11C7/22

Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.