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    1.
    发明专利
    未知

    公开(公告)号：DE602005015336D1

    公开(公告)日：2009-08-20

    申请号：DE602005015336

    申请日：2005-08-19

    Applicant: IBM

    Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

    IPC: G11C7/22

    Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

    2.
    发明专利
    未知

    公开(公告)号：DE69031530D1

    公开(公告)日：1997-11-06

    申请号：DE69031530

    申请日：1990-10-17

    Applicant: IBM

    Inventor： LYFORD AVERY MARTIN ,  MOELLER DENNIS LEE ,  KLIM PETER JUERGEN

    IPC: G06F9/48 ,  G06F13/24 ,  G06F13/26

    Abstract: A programmable interrupt controller (8) having a plurality of interrupt request inquest inputs (42, 56)and an interrupt request output (58) for connection to a central processing unit (4) (CPU) includes means for interrupting the CPU (4) over the interrupt request output (58) responsive to an interrupt request from any one of the interrupt request inputs (42, 56) and a priority resolver (92) for assigning a priority position to each of the interrupt request inputs (42, 56) to create an interrupt priority hierarchy. The interrupt controller (8) is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register (94) of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register (94) to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

    PROGRAMMABLE INTERRUPT CONTROLLER
    3.
    发明专利
    PROGRAMMABLE INTERRUPT CONTROLLER 未知

    公开(公告)号：AU6375790A

    公开(公告)日：1991-05-09

    申请号：AU6375790

    申请日：1990-10-03

    Applicant: IBM

    Inventor： LYFORD AVERY MARTIN ,  MOELLER DENNIS LEE ,  KLIM PETER JUERGEN

    IPC: G06F9/48 ,  G06F13/24 ,  G06F13/26 ,  G06F13/36

    Abstract: A programmable interrupt controller (8) having a plurality of interrupt request inquest inputs (42, 56)and an interrupt request output (58) for connection to a central processing unit (4) (CPU) includes means for interrupting the CPU (4) over the interrupt request output (58) responsive to an interrupt request from any one of the interrupt request inputs (42, 56) and a priority resolver (92) for assigning a priority position to each of the interrupt request inputs (42, 56) to create an interrupt priority hierarchy. The interrupt controller (8) is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register (94) of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register (94) to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

    4.
    发明专利
    未知

    公开(公告)号：AT436073T

    公开(公告)日：2009-07-15

    申请号：AT05779156

    申请日：2005-08-19

    Applicant: IBM

    Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

    IPC: G11C7/22

    Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

    ELIMINATION OF SOI PARASITIC BIPOLAR EFFECT.
    5.
    发明专利
    ELIMINATION OF SOI PARASITIC BIPOLAR EFFECT. 未知

    公开(公告)号：MY124622A

    公开(公告)日：2006-06-30

    申请号：MYPI9904529

    申请日：1999-10-20

    Applicant: IBM

    Inventor： CIRAULA MICHAEL KEVIN ,  DURHAM CHRISTOPHER MCCALL ,  KLIM PETER JUERGEN

    IPC: H01L27/00 ,  H03K17/16 ,  H01L27/06 ,  H03K19/003 ,  H03K19/096

    Abstract: THE PRESENT INVENTION ADDRESSES THE FOREGOING NEEDS BY PROVIDING A CIRCUIT IMPLEMENTED IN SOI (SILICON ON INSULATOR) CMOS, WHICH INCLUDES A FIRST NODE (311) PRECHARGED TO AN ACTIVATED LEVEL, A FIRST TRANSISTOR (310, 315, 320) COUPLED BETWEEN THE FIRST NODE AND THE SECOND NODE (312- 314), A SECOND TRANSISTOR (309, 316, 319) COUPLED BETWEEN THE SECOND NODE AND A GROUND POTENTIAL, AND A THIRD TRANSISTOR (325-327) COUPLED TO THE SECOND NODE AND OPERABLE FOR PREVENTING THE SECOND NODE FROM RISING TO THE ACTIVATED LEVEL. THE THIRD TRANSISTOR PREVENTS THE PARASITIC BIPOLAR EFFECT FROM RAISING THIS SECOND NODE TO THE ACTIVATED LEVEL. ESSENTIALLY, THE THIRD TRANSISTOR MAINTAINS THE SECOND NODE SUBSTANTIALLY AT A GROUND LEVEL.(FIG. 3)

    APARATO DE ARCHIVO DE REGISTRO Y METODO QUE INCORPORA BLOQUEO DE LECTURA-DESPUES-DE-ESCRITURA UTILIZANDO CELDAS DE DETECCION.
    7.
    发明专利
    APARATO DE ARCHIVO DE REGISTRO Y METODO QUE INCORPORA BLOQUEO DE LECTURA-DESPUES-DE-ESCRITURA UTILIZANDO CELDAS DE DETECCION. 未知

    公开(公告)号：MX2007002013A

    公开(公告)日：2007-03-28

    申请号：MX2007002013

    申请日：2005-08-19

    Applicant: IBM

    Inventor： CHU SAM-GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

    IPC: G11C7/00

    Abstract: Un aparato y metodo de archivo de registro que incorpora bloqueo de lectura-despues-de escritura utilizando celdas de deteccion proporciona tiempos de acceso de lectura mejorados en archivos de registro de alto rendimiento. Una o mas celdas de deteccion identicas a las celdas del archivo de registro y ubicadas en el arreglo de archivos de registro se utilizan para controlar la operacion de lectura en el archivo de registro al configurar las celdas de deteccion ya sea aun valor alterno en cada escritura o cambio a un valor particular despues de una escritura y luego detectar cuando la escritura se ha completado al detectar el cambio de estado de una celda de deteccion activa. La deteccion del cambio de estado puede emplearse para retrasar el borde delantero de un estrobo del lectura o puede utilizarse en la logica de control de acceso para retrasar la generacion de un siguiente estrobo de lectura. El archivo de registro de esta manera proporciona un diseno ajustable en escala que no tiene que afinarse para cada aplicacion y que da seguimiento localiza sobre la variacion de sesgo de reloj y voltaje.

    REGISTER FILE APPARATUS AND METHOD INCORPORATING READ-AFTER-WRITE BLOCKING USING DETECTION CELLS
    8.
    发明专利
    REGISTER FILE APPARATUS AND METHOD INCORPORATING READ-AFTER-WRITE BLOCKING USING DETECTION CELLS 未知

    公开(公告)号：CA2577272A1

    公开(公告)日：2006-02-23

    申请号：CA2577272

    申请日：2005-08-19

    Applicant: IBM

    Inventor： CHU SAM GAT-SHANG ,  KLIM PETER JUERGEN ,  LEE MICHAEL JU HYEOK ,  PAREDES JOSE ANGEL

    IPC: G11C7/22

    Abstract: A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

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