公开(公告)号：GB2573450B

公开(公告)日：2021-10-06

申请号：GB201910103

申请日：2018-01-09

Applicant: IBM

Inventor： WANKI KIM ,  CHUNG HON LAM ,  ROBERT BRUCE ,  FABIO CARTA

IPC: H01L45/00 ,  H01L21/82 ,  H01L27/24

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

公开(公告)号：GB2573450A

公开(公告)日：2019-11-06

申请号：GB201910103

申请日：2018-01-09

Applicant: IBM

Inventor： WANKI KIM ,  CHUNG HON LAM ,  ROBERT BRUCE ,  FABIO CARTA

IPC: H01L45/00 ,  H01L21/82 ,  H01L27/24

Abstract: A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

公开(公告)号：GB2608320A

公开(公告)日：2022-12-28

申请号：GB202213458

申请日：2021-02-17

Applicant: IBM

Inventor： NING LI ,  WANKI KIM ,  STEPHEN BEDELL ,  DEVENDRA SADANA

IPC: G11C11/00 ,  G11C7/00

Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.