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    Cache performance improvement through the use of early select techniques and pipelining
    2.
    发明专利
    Cache performance improvement through the use of early select techniques and pipelining 未知

    公开(公告)号：GB2328298B

    公开(公告)日：2002-02-20

    申请号：GB9814444

    申请日：1998-07-06

    Applicant: IBM

    Inventor： MATICK RICHARD EDWARD ,  SCHUSTER STANLEY EVERETT

    IPC: G06F12/08

    Abstract: A DRAM for L2 cache is used in a computer memory hierarchy without compromising overall system performance. By proper organization and design, the DRAM L2 cache is many times larger than a SRAM implementation in the same technology, but without compromising overall system performance. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time. To achieve this, it is essential to minimize the total DRAM access time as much as possible by the use of early select techniques and pipelining.

    3.
    发明专利
    未知

    公开(公告)号：DE3483495D1

    公开(公告)日：1990-12-06

    申请号：DE3483495

    申请日：1984-04-25

    Applicant: IBM

    Inventor： DILL FREDERICK HAYES ,  LING DANIEL TAJEN ,  MATICK RICHARD EDWARD ,  MCBRIDE DENNIS JAY

    IPC: G06F12/00 ,  G06F12/06 ,  G06F12/08 ,  G06F13/38 ,  G06F15/167 ,  G06F15/16

    Abstract: A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer means connected in between the first and second bit arrays of each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A control means is located on each chip and connected to the first and second memory arrays and the M bit buffer means for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.

    6.
    发明专利
    未知

    公开(公告)号：IT1149266B

    公开(公告)日：1986-12-03

    申请号：IT2597380

    申请日：1980-11-14

    Applicant: IBM

    Inventor： EARDLEY DAVID BARRY ,  MATICK RICHARD EDWARD

    IPC: G11C11/414 ,  G11C8/16 ,  G11C11/411 ,  G11C

    Abstract: A random access memory system is disclosed in which data stored in two distinct memory locations defined by distinct address signals can be non-destructively read out simultaneously. The system employs a matrix of two-port memory cells (21), each cell functioning to store one binary bit of data in a conventional cross-coupled common emitter flip-flop. A pair of input/output transistors (T z , T 3 ) have their emitters connected to the respective control nodes (A, B) of the static cell, their bases connected to first (WLO) and second word lines (WL1), and their collectors connected to first (BSO) and second (BS1) bit sense lines. The word lines and bit lines are addressed and pulsed such that during reading of the selected cells, current flows through only one of the input transistors of one of the cells to a sense line whereon, during writing, current flows through both of the input/output transistors, the direction of current flow during writing depending on the value of the binary bit being stored. The input/output transistors associated with each cell are integrated onto the chip and occupy only slightly more area than multi-configured devices conventionally employed in prior art two-port cells.

    Cache performance improvement through the use of early select techniques and pipelining
    7.
    发明专利
    Cache performance improvement through the use of early select techniques and pipelining 未知

    公开(公告)号：GB2328298A

    公开(公告)日：1999-02-17

    申请号：GB9814444

    申请日：1998-07-06

    Applicant: IBM

    Inventor： MATICK RICHARD EDWARD ,  SCHUSTER STANLEY EVERETT

    IPC: G06F12/08

    Abstract: A computer memory hierarchy comprises a level one (L1) cache with access/cycle time equal to or faster than a processor cycle time which can deliver at least a logical word or words needed by the processor on each cycle for an L1 HIT and an L2 cache including a directory and data array in which the L2 directory is accessed upon a MISS to the L1 cache. The L2 data array has a mapping from the L2 directory to the data array such that one block needs to be accessed from the data array, the L2 directory performing required address translation and, upon a HIT, starting access to the L2 array for a specific block required for reloading into the L1 cache, and upon a MISS, the L2 cache requesting a block reload from a next level of the hierarchy. The invention allows a DRAM L2 cache to be used in a computer memory hierarchy without compromising overall system performance. To achieve this, the total DRAM access is minimised as much as possible by use of early select techniques and pipelining. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time.

    8.
    发明专利
    未知

    公开(公告)号：DE3585932D1

    公开(公告)日：1992-06-04

    申请号：DE3585932

    申请日：1985-05-10

    Applicant: IBM

    Inventor： CHUNG PAUL WING-SHING ,  MATICK RICHARD EDWARD ,  LING DANIEL TAJEN

    IPC: G11C11/401 ,  G06F12/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/00 ,  G11C11/409

    Abstract: A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.

    CIRCUITS FOR ACCESSING A VARIABLE WIDTH DATA BUS WITH A VARIABLE WIDTH DATA FIELD
    9.
    发明专利
    CIRCUITS FOR ACCESSING A VARIABLE WIDTH DATA BUS WITH A VARIABLE WIDTH DATA FIELD 未知

    公开(公告)号：DE3380572D1

    公开(公告)日：1989-10-19

    申请号：DE3380572

    申请日：1983-06-01

    Applicant: IBM

    Inventor： DILL FREDERICK HAYES ,  LING DANIEL TAJEN ,  MATICK RICHARD EDWARD ,  MCBRIDE DENNIS JAY

    IPC: G06F13/36 ,  G06F5/00 ,  G06F5/01 ,  G06F7/76 ,  G06F13/40

    Abstract: A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N c and a data field of N f , the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. Structure includes a modulo N c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N c . A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.

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