公开(公告)号：US3909808A

公开(公告)日：1975-09-30

申请号：US53574874

申请日：1974-12-23

Applicant: IBM

Inventor： COCHRAN WILLIAM HUGH ,  HEUER DALE ARTHUR ,  SHEEHAN MICHAEL JAMES

IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C17/12 ,  H03M7/00 ,  G11C11/40

CPC classification number: G11C17/12 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  H03M7/00

Abstract: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

Abstract translation: MOSFET解码器电路配置，通过以比传统解码器电路更窄的间距提供解码输出线来增强读/存储存储器密度，从而增加常规解码器的解码线数。 此外，所需的常规解码器电路的数量由二进制因子减少，从而降低功率需求。 通过适当寻址的阵列选择装置增加解码线路能力，由此所需的阵列选择装置的数量等于所使用的特定二进制因子。 对于在本发明的集成解码器的制造中使用的特定物理布局基础规则，选择二进制因子，使得解码器间距等于读/存储存储器间距，以获得最大的码片密度。

公开(公告)号：CH594319A5

公开(公告)日：1978-01-13

申请号：CH1601775

申请日：1975-12-10

Applicant: IBM

Inventor： COCHRAN WILLIAM HUGH ,  HEUER DALE ARTHUR ,  SHEEHAN MICHAEL JAMES

IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C17/12 ,  H03M7/00 ,  H03K13/00

Abstract: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

公开(公告)号：DE3174875D1

公开(公告)日：1986-07-31

申请号：DE3174875

申请日：1981-07-06

Applicant: IBM

Inventor： COCHRAN WILLIAM HUGH ,  WU PHILIP TUNG

IPC: G11C14/00 ,  G11C7/20 ,  G11C11/00 ,  G11C11/24 ,  G11C17/00

公开(公告)号：DE2557006A1

公开(公告)日：1976-07-08

申请号：DE2557006

申请日：1975-12-18

Applicant: IBM

Inventor： COCHRAN WILLIAM HUGH ,  HEUER DALE ARTHUR ,  SHEEHAN MICHAEL JAMES

IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C17/12 ,  H03M7/00 ,  G11C7/00

Abstract: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

公开(公告)号：DE2354520A1

公开(公告)日：1974-06-20

申请号：DE2354520

申请日：1973-10-31

Applicant: IBM

Inventor： COCHRAN WILLIAM HUGH ,  HEILING GERALD MICHAEL

IPC: G06K7/10 ,  G06K9/20 ,  H04N1/401 ,  H04N1/38

Abstract: A self-scanned photodiode array operating in the recharge current mode generates a serial video information output signal as light from a light emitting diode illuminator is reflected from the scanned document and imaged onto the photodiode array. A photodiode sensitivity and illumination variance compensation signal is generated during a write mode as the photodiode array scans a white background. The serial compensation signal thus generated is converted into an N bit binary code for each photodiode in the array. The N bit binary code is stored. Thereafter, when scanning printed or written information on the document during an operational mode, the serial video information signal is digitized as in the write mode and forms an address together with the stored digitized compensation bits for addressing a stored table of normalized contrast ratios in the form of M data bits. These M data bits are passed to an output buffer and converted to an analog signal equal to 1 minus the contrast ratio to provide a corrected serial video information signal.