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    Minimum pitch mosfet decoder circuit configuration
    1.
    发明授权
    Minimum pitch mosfet decoder circuit configuration 失效
    最小间距mosfet解码器电路配置

    公开(公告)号：US3909808A

    公开(公告)日：1975-09-30

    申请号：US53574874

    申请日：1974-12-23

    Applicant: IBM

    Inventor： COCHRAN WILLIAM HUGH ,  HEUER DALE ARTHUR ,  SHEEHAN MICHAEL JAMES

    IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C17/12 ,  H03M7/00 ,  G11C11/40

    CPC classification number: G11C17/12 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  H03M7/00

    Abstract: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

    Abstract translation: MOSFET解码器电路配置，通过以比传统解码器电路更窄的间距提供解码输出线来增强读/存储存储器密度，从而增加常规解码器的解码线数。 此外，所需的常规解码器电路的数量由二进制因子减少，从而降低功率需求。 通过适当寻址的阵列选择装置增加解码线路能力，由此所需的阵列选择装置的数量等于所使用的特定二进制因子。 对于在本发明的集成解码器的制造中使用的特定物理布局基础规则，选择二进制因子，使得解码器间距等于读/存储存储器间距，以获得最大的码片密度。

    2.
    发明专利
    未知

    公开(公告)号：CH594319A5

    公开(公告)日：1978-01-13

    申请号：CH1601775

    申请日：1975-12-10

    Applicant: IBM

    Inventor： COCHRAN WILLIAM HUGH ,  HEUER DALE ARTHUR ,  SHEEHAN MICHAEL JAMES

    IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C17/12 ,  H03M7/00 ,  H03K13/00

    Abstract: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

    7.
    发明专利
    未知

    公开(公告)号：CH620779A5

    公开(公告)日：1980-12-15

    申请号：CH544977

    申请日：1977-05-02

    Applicant: IBM

    Inventor： HEUER DALE ARTHUR ,  SCHLOSS PHILLIP CHRISTIAN ,  SCHROEDER LARRY LLOYD

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/508 ,  G06F9/22 ,  G06F9/30 ,  G06F12/00 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F15/78 ,  G06F13/00 ,  G06F9/28

    Abstract: A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

    8.
    发明专利
    未知

    公开(公告)号：DE2557006A1

    公开(公告)日：1976-07-08

    申请号：DE2557006

    申请日：1975-12-18

    Applicant: IBM

    Inventor： COCHRAN WILLIAM HUGH ,  HEUER DALE ARTHUR ,  SHEEHAN MICHAEL JAMES

    IPC: G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C17/12 ,  H03M7/00 ,  G11C7/00

    Abstract: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

    MICROPROCESSOR SYSTEM
    10.
    发明专利
    MICROPROCESSOR SYSTEM 未知

    公开(公告)号：AU2478977A

    公开(公告)日：1978-11-09

    申请号：AU2478977

    申请日：1977-05-02

    Applicant: IBM

    Inventor： HEUER DALE ARTHUR ,  SCHROEDER LARRY LLOYD ,  SCHLOSS PHILLIP CHRISTIAN

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/508 ,  G06F9/22 ,  G06F9/30 ,  G06F12/00 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F15/78 ,  G06F9/06 ,  G06F13/06

    Abstract: A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

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