公开(公告)号：AU8100675A

公开(公告)日：1976-11-11

申请号：AU8100675

申请日：1975-05-09

Applicant: IBM

Inventor： CORDI VINCENT ANTHONY ,  EDSON BRUCE ADAM

IPC: G06F13/00 ,  G06F11/14 ,  G06F12/08 ,  G06F12/16 ,  G06F11/00 ,  G11C7/00 ,  G11C29/00

Abstract: This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.

公开(公告)号：DE2404259A1

公开(公告)日：1974-08-08

申请号：DE2404259

申请日：1974-01-30

Applicant: IBM

Inventor： CORDI VINCENT ANTHONY ,  GURSKI CHESTER STANLEY

IPC: G06K17/00 ,  G06F7/06 ,  G06F13/00

公开(公告)号：DE2523414A1

公开(公告)日：1976-01-22

申请号：DE2523414

申请日：1975-05-27

Applicant: IBM

Inventor： CORDI VINCENT ANTHONY ,  EDSON BRUCE ADAM

IPC: G06F13/00 ,  G06F11/14 ,  G06F12/08 ,  G06F12/16

Abstract: This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.

公开(公告)号：DE2310631A1

公开(公告)日：1973-10-18

申请号：DE2310631

申请日：1973-03-02

Applicant: IBM

Inventor： CORDI VINCENT ANTHONY ,  NICKEL TED YOUNG

IPC: G06F12/08 ,  G06F12/12 ,  G11C19/08 ,  G06F13/00

Abstract: A Least Recently Used (LRU) Algorithm is implemented in a dynamically ordered, magnetic bubble domain shift register to enhance both the speed and cost reduction of paging between levels of a storage hierarchy containing a large quantity of data.

公开(公告)号：DE2456709A1

公开(公告)日：1975-07-10

申请号：DE2456709

申请日：1974-11-30

Applicant: IBM

Inventor： BOSSEN DOUGLAS CRAIG ,  CORDI VINCENT ANTHONY ,  GLICK ELLIS WILLIAM ,  HSIAO MU-YUE ,  SHIFFRIN BARRY NORMAN

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03K13/32

Abstract: An error correction and detection circuit includes a modular encoder that provides the minimum number of check bits for encoding a particular number of data bits. Means is provided for combining several units to produce the minimum number of code bits when a larger data word is to be encoded. A storage hierarchy system using this error correction circuit is also disclosed.

公开(公告)号：DE2454745A1

公开(公告)日：1975-07-10

申请号：DE2454745

申请日：1974-11-19

Applicant: IBM

Inventor： CORDI VINCENT ANTHONY ,  GURSKI CHESTER STANLEY

IPC: G06F11/16 ,  H03K21/40 ,  H03K21/34

Abstract: This specification discloses a binary counter with two channels each consisting of a binary counter with ripple carry. Both channels store the same binary number, and to advance the count, a pulse is first applied to the input to one counter and thereafter applied to the input of the other counter. The output of each stage in one counter is Exclusive Ored with the output of the same stage in the other counter. The results of this Exclusive ORing is analyzed with additional logic circuitry to determine if the counts in the two channels are or are not equal. If they are not equal the analysis determines which of the counters contains the higher count, and if the difference in the counts is greater than one. This information is then used to find which of the channels is in error and whether the error is a transient error or an error resulting from a hard failure in one of the channels.