公开(公告)号：WO02099873A3

公开(公告)日：2003-09-18

申请号：PCT/EP0205282

申请日：2002-05-14

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： AGARWALA BIRENDRA N ,  COKER ERIC M ,  CORREALE ANTHONY JR ,  RATHORE HAZARA S ,  SULLIVAN TIMOTHY D

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure, comprising: a lower level wire (200) having a side and a bottom, the lower level wire comprising: a lower core conductor (220) and a lower conductive liner (215), the lower conductive liner on the side and the bottom of the lower level wire; an upper level (205) wire having a side and a bottom, the upper level wire comprising an upper core conductor (230) and an upper conductive liner (225), the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region (240A), (240B).

Abstract translation: 一种互连结构，包括：具有侧面和底部的下层导线（200），所述下层导线包括：下芯导体（220）和下导电衬套（215），所述下导电衬垫在侧面，以及 下层电线底部; 具有侧面和底部的上部电缆（205），所述上部电线包括上部芯导体（230）和上部导电衬垫（225），所述上部电线的侧面和底部上的上部导电衬垫 ; 并且所述上导电衬套与所述下芯导体接触并且还在衬套到衬垫接触区域（240A），（240B）中与所述下导电衬垫接触。

公开(公告)号：JP2005160073A

公开(公告)日：2005-06-16

申请号：JP2004335488

申请日：2004-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CORREALE ANTHONY JR ,  JOSHI RAJIV ,  KUNG DAVID S ,  PAN ZHIGANG ,  PURI RUCHIR

IPC: H03K19/0185 ,  H03K19/0948

CPC classification number: H03K19/018521 ,  H03K19/0948

Abstract: PROBLEM TO BE SOLVED: To provide a level converter for interfacing two circuits to which different power supply voltages are supplied, and an integrated circuit containing a level converter interfacing circuits in two different voltage islands.
SOLUTION: Power is supplied to a first buffer 104 with a pretense power supply V, and the first buffer 104 receives an input signal 102 from a lower voltage circuit. The first buffer 104 drives a second buffer 108 to which higher power supply voltage V
ddh is supplied. Power supply selecting mechanisms 120, 128 are so switched by an output 110 from the second buffer 108 that the higher power supply voltage V
ddh or reduced power supply voltage V is selectively passed to the first buffer 104.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种电平转换器，用于连接提供不同电源电压的两个电路，以及包含两个不同电压岛中的电平转换器接口电路的集成电路。 解决方案：用强制电源V向第一缓冲器104供电，第一缓冲器104从较低电压电路接收输入信号102。 第一缓冲器104驱动提供较高电源电压V SB3hh的第二缓冲器108。 电源选择机构120,128由来自第二缓冲器108的输出110进行切换，使得较高的电源电压V SB =或降低的电源电压V被选择性地传递到第一缓冲器104。 P>版权所有（C）2005，JPO＆NCIPI

公开(公告)号：DE69021683D1

公开(公告)日：1995-09-21

申请号：DE69021683

申请日：1990-09-21

Applicant: IBM

Inventor： CORREALE ANTHONY JR ,  DONEY RICHARD MICHAEL ,  O'DONNELL KIM EDWARD ,  KEGL ANDREW ,  TATE ERWIN ARTHUR ,  WU DAVID M

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26

Abstract: The present invention implements self testable boundary logic by using a tristate pass gate (60)and a tristate receiver (70)in combination with a linear feedback shift register (30), a storage register (120), and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.

公开(公告)号：AU2002314065A1

公开(公告)日：2002-12-16

申请号：AU2002314065

申请日：2002-05-14

Applicant: IBM

Inventor： COKER ERIC M ,  RATHORE HAZARA S ,  CORREALE ANTHONY JR ,  AGARWALA BIRENDRA N ,  SULLIVAN TIMOTHY D

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

公开(公告)号：DE69021683T2

公开(公告)日：1996-04-18

申请号：DE69021683

申请日：1990-09-21

Applicant: IBM

Inventor： CORREALE ANTHONY JR ,  DONEY RICHARD MICHAEL ,  O'DONNELL KIM EDWARD ,  KEGL ANDREW ,  TATE ERWIN ARTHUR ,  WU DAVID M

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26

Abstract: The present invention implements self testable boundary logic by using a tristate pass gate (60)and a tristate receiver (70)in combination with a linear feedback shift register (30), a storage register (120), and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.