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    DUAL DAMASCENE MULTI-LEVEL METALLIZATION
    1.
    发明申请
    DUAL DAMASCENE MULTI-LEVEL METALLIZATION 审中-公开
    双重DAMASCENE多级金属化

    公开(公告)号：WO02099873A3

    公开(公告)日：2003-09-18

    申请号：PCT/EP0205282

    申请日：2002-05-14

    Applicant: IBM ,  IBM DEUTSCHLAND

    Inventor： AGARWALA BIRENDRA N ,  COKER ERIC M ,  CORREALE ANTHONY JR ,  RATHORE HAZARA S ,  SULLIVAN TIMOTHY D

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure, comprising: a lower level wire (200) having a side and a bottom, the lower level wire comprising: a lower core conductor (220) and a lower conductive liner (215), the lower conductive liner on the side and the bottom of the lower level wire; an upper level (205) wire having a side and a bottom, the upper level wire comprising an upper core conductor (230) and an upper conductive liner (225), the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region (240A), (240B).

    Abstract translation: 一种互连结构，包括：具有侧面和底部的下层导线（200），所述下层导线包括：下芯导体（220）和下导电衬套（215），所述下导电衬垫在侧面，以及 下层电线底部; 具有侧面和底部的上部电缆（205），所述上部电线包括上部芯导体（230）和上部导电衬垫（225），所述上部电线的侧面和底部上的上部导电衬垫 ; 并且所述上导电衬套与所述下芯导体接触并且还在衬套到衬垫接触区域（240A），（240B）中与所述下导电衬垫接触。

    FORMATION METHOD OF VIA STUD, AND SEMICONDUCTOR STRUCTURE
    3.
    发明专利
    FORMATION METHOD OF VIA STUD, AND SEMICONDUCTOR STRUCTURE 失效

    公开(公告)号：JP2001351977A

    公开(公告)日：2001-12-21

    申请号：JP2001117713

    申请日：2001-04-17

    Applicant: IBM

    Inventor： DALAL HORMAZDYAR M ,  BARENDORA AGARUWARA ,  TERENCE KANE ,  PAUL S MCLOUGHLIN ,  NGUYEN DU ,  RICHARD PROCTER ,  RATHORE HAZARA S ,  YUN-YUU WONG

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnection part that has an improved electromigration life. SOLUTION: This formation method of a via stud includes a process that prepares a substrate 10 having first level adhesion metal 20 (a), a process that allows a layer 35 of an insulator to adhere (b), and a process that etches the insulator by a first etchant to form a related level. The related level has a line opening 33 and a via opening 34. Etching by the first etchant exposes the first level metal at the lower side of the via opening and includes a process that etches the exposed first level metal, so that the opening is formed (d) and a process that allows a linear 51 to adhere (e). The liner lines nearly the entire bottom part of the exposed first level metal and nearly the entire sidewall of the opening of the related level other than the nearly the entire sidewall of the first level metal.

    COPPER INTERCONNECTION OF SUB-QUARTER MICRON REDUCING DEGREE OF INFLUENCE FROM DEFECT-ENHANCING ELECTRO-MIGRATION RESISTANCE
    4.
    发明专利
    COPPER INTERCONNECTION OF SUB-QUARTER MICRON REDUCING DEGREE OF INFLUENCE FROM DEFECT-ENHANCING ELECTRO-MIGRATION RESISTANCE 失效

    公开(公告)号：JPH1145887A

    公开(公告)日：1999-02-16

    申请号：JP14391498

    申请日：1998-05-26

    Applicant: IBM

    Inventor： RATHORE HAZARA S ,  DALAL HORMAZDYAR M ,  PAUL S MCLAUGHLIN ,  NGUYEN DU B ,  SMITH RICHARD G ,  SWINTON ALEXANDER J ,  WACHNIK RICHARD A

    IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To form performance interconnection circuit having a high dimension of sub-half micron having enhanced processing yield and reliability by a method wherein a multilayered interconnection of a copper wire separated from each other by a dielectric insulation is formed, and a contact part with an electrical mechanism in a substrate is formed. SOLUTION: A thin layer 7 of an element, capable of forming a compound between copper and a metal which preferably has a thickness of about 100 to 600 angstroms is adhered to an arbitrarily selected layer 6, and thereafter a thin copper seed layer 8 of a thickness of about 600 to 2000 angstroms is typically stacked. A remaining copper layer 9 is electrically plated after the copper seed layer 8 to bury a groove, or the layer 8, or the layer 8 and the layer 9, may be stacked by a CVD method. Next, this substrate wafer is polished by a chemical mechanical method and all extra metals are removed from a region in which a pattern is not drawn to thereby make a flat structure.

    Dual damascene multi-level metallization
    7.
    发明专利
    Dual damascene multi-level metallization 未知

    公开(公告)号：AU2002314065A1

    公开(公告)日：2002-12-16

    申请号：AU2002314065

    申请日：2002-05-14

    Applicant: IBM

    Inventor： COKER ERIC M ,  RATHORE HAZARA S ,  CORREALE ANTHONY JR ,  AGARWALA BIRENDRA N ,  SULLIVAN TIMOTHY D

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

    Abstract: A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

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