公开(公告)号：WO02099873A3

公开(公告)日：2003-09-18

申请号：PCT/EP0205282

申请日：2002-05-14

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： AGARWALA BIRENDRA N ,  COKER ERIC M ,  CORREALE ANTHONY JR ,  RATHORE HAZARA S ,  SULLIVAN TIMOTHY D

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure, comprising: a lower level wire (200) having a side and a bottom, the lower level wire comprising: a lower core conductor (220) and a lower conductive liner (215), the lower conductive liner on the side and the bottom of the lower level wire; an upper level (205) wire having a side and a bottom, the upper level wire comprising an upper core conductor (230) and an upper conductive liner (225), the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region (240A), (240B).

Abstract translation: 一种互连结构，包括：具有侧面和底部的下层导线（200），所述下层导线包括：下芯导体（220）和下导电衬套（215），所述下导电衬垫在侧面，以及 下层电线底部; 具有侧面和底部的上部电缆（205），所述上部电线包括上部芯导体（230）和上部导电衬垫（225），所述上部电线的侧面和底部上的上部导电衬垫 ; 并且所述上导电衬套与所述下芯导体接触并且还在衬套到衬垫接触区域（240A），（240B）中与所述下导电衬垫接触。

公开(公告)号：CA2084685C

公开(公告)日：1996-01-16

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/488 ,  H01L23/50

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier (12) a pad (14) is formed on which a solder mass (16) is deposited and capped with a metal layer (19), thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass (26) on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：AU2002360420A1

公开(公告)日：2003-07-30

申请号：AU2002360420

申请日：2002-11-22

Applicant: IBM

Inventor： WANG YUN YU ,  GATES STEPHEN ,  AGARWALA BIRENDRA N ,  FITZSIMMONS JOHN A ,  LEE JIA ,  LUSTIG NAFTALI E

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L21/469 ,  H01L21/4763

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k). The cap layer is formed of amorphous nitrogenated hydrogenated silicon cabride, and has a dielectric constant (k) of less than about 5. A method for forming the BEOL metallization structure is also disclosed, where the cap layer is deposited using a plasma-enhanced chemical vapor deposition (PE CVD) process. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：AU2002314065A1

公开(公告)日：2002-12-16

申请号：AU2002314065

申请日：2002-05-14

Applicant: IBM

Inventor： COKER ERIC M ,  RATHORE HAZARA S ,  CORREALE ANTHONY JR ,  AGARWALA BIRENDRA N ,  SULLIVAN TIMOTHY D

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

公开(公告)号：CA2084685A1

公开(公告)日：1991-12-20

申请号：CA2084685

申请日：1990-10-16

Applicant: IBM

Inventor： AGARWALA BIRENDRA N ,  AHSAN AZIZ M ,  BROSS ARTHUR ,  CHADURJIAN MARK F ,  KOOPMAN NICHOLAS G ,  LEE LI-CHUNG ,  PUTTLITZ KARL J ,  RAY SUDIPTA K ,  RYAN JAMES G ,  SCHAEFER JOSEPH G ,  SRIVASTAVA KAMALESH K ,  TOTTA PAUL A ,  WALTON ERICK G ,  WIRSING ADOLF E

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.