公开(公告)号：DE3779313D1

公开(公告)日：1992-06-25

申请号：DE3779313

申请日：1987-08-20

Applicant: IBM

Inventor： COSTES MICHEL ,  GACH ALAIN ,  HARTMANN YVES ,  PEYRONNENC MICHEL

IPC: G06F13/28 ,  G06F13/42

Abstract: A receiver (34) and inverter (38) in a line adapter (5) cooperate for receiving a DMA clock signal on a DMA clock line (28) and for outputting an adapter clock signal, derived from the DMA clock signal, on an adapter clock line (36). Control and sampling logic (22) in a DMA controller responds to an AND gate (5e) which receives a transfer request signal on a request line (44) from the adapter and an inverted disable signal sent from the adapter (5). When the request is able to be serviced by a first input-output device the controller sends a transfer control signal on a bus (R/W 62).