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公开(公告)号：DE3782335D1
公开(公告)日：1992-11-26
申请号：DE3782335
申请日：1987-04-22
Applicant: IBM
Inventor： GACH ALAIN , HARTMANN YVES , PEYRONNENC MICHEL
IPC: G06F12/0831 , G06F13/16 , G06F13/28 , G06F13/30 , G06F13/34
Abstract: A processor request buffered into a processor controller (20) is serviced immediately if the memory controller (24) is available. Otherwise a direct memory access request in the course of servicing by the DMA controller (22) is interrupted while the processor request is dealt with. Write requests are acknowledged that the requesting processor can resume execution without awaiting completion of memory update. A read request which does not hit the cache is sent to the processor controller (20) for cache update. The DMA controller (24) includes buffer storage (80) for data bursts.
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公开(公告)号：DE3782500T2
公开(公告)日：1993-05-06
申请号：DE3782500
申请日：1987-12-23
Applicant: IBM
Inventor： GLAISE RENE , HARTMANN YVES , HUON PIERRE , PEYRONNENC MICHEL
Abstract: The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended.
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公开(公告)号：DE3874518D1
公开(公告)日：1992-10-15
申请号：DE3874518
申请日：1988-01-22
Applicant: IBM
Inventor： MUNIER JEAN-MARC , PEYRONNENC MICHEL , PORET MICHEL
Abstract: The subject mechanism 38 is implemented in a passive device 30 inserted on a synchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto which data are transferred between the two devices under control of tag lines and clock signals on lines 20 and 22, which are companion of the transferred data. It allows errors to be detected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the error signals to be reported in a pseudo synchronous way on error bus 50, thanks to error detection and reporting logic circuit 48 and pseudo syncho timing circuit 52.
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公开(公告)号：DE3874518T2
公开(公告)日：1993-04-08
申请号：DE3874518
申请日：1988-01-22
Applicant: IBM
Inventor： MUNIER JEAN-MARC , PEYRONNENC MICHEL , PORET MICHEL
Abstract: The subject mechanism 38 is implemented in a passive device 30 inserted on a synchronous bus 1, linking two devices 2 and 4. The bus comprises data lines 6 onto which data are transferred between the two devices under control of tag lines and clock signals on lines 20 and 22, which are companion of the transferred data. It allows errors to be detected and the failing device, i.e. 2, 4, 30, 1-1 or 1-2 to be identified and the error signals to be reported in a pseudo synchronous way on error bus 50, thanks to error detection and reporting logic circuit 48 and pseudo syncho timing circuit 52.
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Patent Agency Ranking
公开(公告)号：DE3779313D1
公开(公告)日：1992-06-25
申请号：DE3779313
申请日：1987-08-20
Applicant: IBM
Inventor： COSTES MICHEL , GACH ALAIN , HARTMANN YVES , PEYRONNENC MICHEL
Abstract: A receiver (34) and inverter (38) in a line adapter (5) cooperate for receiving a DMA clock signal on a DMA clock line (28) and for outputting an adapter clock signal, derived from the DMA clock signal, on an adapter clock line (36). Control and sampling logic (22) in a DMA controller responds to an AND gate (5e) which receives a transfer request signal on a request line (44) from the adapter and an inverted disable signal sent from the adapter (5). When the request is able to be serviced by a first input-output device the controller sends a transfer control signal on a bus (R/W 62).
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公开(公告)号：DE3782335T2
公开(公告)日：1993-05-06
申请号：DE3782335
申请日：1987-04-22
Applicant: IBM
Inventor： GACH ALAIN , HARTMANN YVES , PEYRONNENC MICHEL
IPC: G06F12/0831 , G06F13/16 , G06F13/28 , G06F13/30 , G06F13/34
Abstract: The memory control subsystem controls and arbitrates the access to a memory 10 which is shared by a plurality of users comprising at least a processor 2 with its cache and input/output devices 4 having direct access to the memory through a direct memory access bus 12. It comprises a processor controller 20, a DMA controller 22 and a memory controller 24. A processor request is buffered into the processor controller 20 and is serviced right away if the memory controller is available, possibly with a simulataneous transfer between the devices 4 and buffers in the DMA controller 22. If the memory controller 24 is busy, because a DMA request is being serviced, the DMA controller comprises means to cause the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards. Write requests made by the processor are buffered into processor controller 20 and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion. A read request which does not hit the cache is sent to the processor controller which causes the cache to be updated. In case of multiple processor requests contending with a long DMA transfer, the latter is sliced into several parts, each part mapping one cache line. In case of a DMA write, the cache lines which correspond to memory positions whose content is modified by the write operation are invalidated in such a way that the processor cannot read a partially written line into the cache.
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公开(公告)号：CA1299764C
公开(公告)日：1992-04-28
申请号：CA569055
申请日：1988-06-09
Applicant: IBM
Inventor： GLAISE RENE , HARTMANN YVES , HUON PIERRE , PEYRONNENC MICHEL
Abstract: FR 9 87 018 EFFICIENT INTERFACE FOR THE MAIN STORE OF A DATA PROCESSING SYSTEM The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended. (Figure 1)
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公开(公告)号：DE3786080D1
公开(公告)日：1993-07-08
申请号：DE3786080
申请日：1987-08-20
Applicant: IBM
Inventor： DEBIZE JEAN-CLAUDE , HARTMANN YVES , HUON PIERRE , PEYRONNENC MICHEL
Abstract: The processor (14) initiates data transfer to or from a selected input-output device on a processor bus (18) by sending a receive or transmit command and the starting address and burst length allocated in memory to the input-output device, to the memory format adapter (10) on the data bus (22). For controlling the input-output device and the memory, the memory format adapter generates read-write controlsignals on a line (24) and byte select control signals and address signals on a respective bus (26,28) to the memory (16). The memory is organised in four-byte words and the data bus is two bytes wide so that the adapter includes alignment and control devices for determining the byte location within the memory words.
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公开(公告)号：DE3782500D1
公开(公告)日：1992-12-10
申请号：DE3782500
申请日：1987-12-23
Applicant: IBM
Inventor： GLAISE RENE , HARTMANN YVES , HUON PIERRE , PEYRONNENC MICHEL
Abstract: The interface mechanism provides one memory request line (11, 12) for each user device and which is activated by the user device when it requests an access to the memory to effect a memory read or write transfer. A last operation line (30), shared by the user devices, is activated by the user device when its memory transfer is complete. An address user indicator line (15,16) and a data user indicator line (17,18) are provided for each user device. An address clock line (26) and a data clock line (28) are shared by the user devices. A memory interface controller (5) responds to the status of memory request lines to select a request from a user device, and to activate the address user and data user indicator lines of the selected device during the periods when the selected device may use the address, data bus. In addition, the controller sends clock pulses for timing transfer of the address and data signals on the respective bus. User interface controls (3-1, 3-2) respond to the controller clock pulses.
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