公开(公告)号：DE3782335D1

公开(公告)日：1992-11-26

申请号：DE3782335

申请日：1987-04-22

Applicant: IBM

Inventor： GACH ALAIN ,  HARTMANN YVES ,  PEYRONNENC MICHEL

IPC: G06F12/0831 ,  G06F13/16 ,  G06F13/28 ,  G06F13/30 ,  G06F13/34

Abstract: A processor request buffered into a processor controller (20) is serviced immediately if the memory controller (24) is available. Otherwise a direct memory access request in the course of servicing by the DMA controller (22) is interrupted while the processor request is dealt with. Write requests are acknowledged that the requesting processor can resume execution without awaiting completion of memory update. A read request which does not hit the cache is sent to the processor controller (20) for cache update. The DMA controller (24) includes buffer storage (80) for data bursts.

公开(公告)号：DE3779313D1

公开(公告)日：1992-06-25

申请号：DE3779313

申请日：1987-08-20

Applicant: IBM

Inventor： COSTES MICHEL ,  GACH ALAIN ,  HARTMANN YVES ,  PEYRONNENC MICHEL

IPC: G06F13/28 ,  G06F13/42

Abstract: A receiver (34) and inverter (38) in a line adapter (5) cooperate for receiving a DMA clock signal on a DMA clock line (28) and for outputting an adapter clock signal, derived from the DMA clock signal, on an adapter clock line (36). Control and sampling logic (22) in a DMA controller responds to an AND gate (5e) which receives a transfer request signal on a request line (44) from the adapter and an inverted disable signal sent from the adapter (5). When the request is able to be serviced by a first input-output device the controller sends a transfer control signal on a bus (R/W 62).

公开(公告)号：DE3782335T2

公开(公告)日：1993-05-06

申请号：DE3782335

申请日：1987-04-22

Applicant: IBM

Inventor： GACH ALAIN ,  HARTMANN YVES ,  PEYRONNENC MICHEL

IPC: G06F12/0831 ,  G06F13/16 ,  G06F13/28 ,  G06F13/30 ,  G06F13/34

Abstract: The memory control subsystem controls and arbitrates the access to a memory 10 which is shared by a plurality of users comprising at least a processor 2 with its cache and input/output devices 4 having direct access to the memory through a direct memory access bus 12. It comprises a processor controller 20, a DMA controller 22 and a memory controller 24. A processor request is buffered into the processor controller 20 and is serviced right away if the memory controller is available, possibly with a simulataneous transfer between the devices 4 and buffers in the DMA controller 22. If the memory controller 24 is busy, because a DMA request is being serviced, the DMA controller comprises means to cause the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards. Write requests made by the processor are buffered into processor controller 20 and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion. A read request which does not hit the cache is sent to the processor controller which causes the cache to be updated. In case of multiple processor requests contending with a long DMA transfer, the latter is sliced into several parts, each part mapping one cache line. In case of a DMA write, the cache lines which correspond to memory positions whose content is modified by the write operation are invalidated in such a way that the processor cannot read a partially written line into the cache.