公开(公告)号：JP2006013114A

公开(公告)日：2006-01-12

申请号：JP2004187616

申请日：2004-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COTTRELL PETER E ,  DENNARD ROBERT H ,  EDWARD J NOWAKU ,  ROHRER NORMAN J

IPC: H01L27/14 ,  G01T1/24 ,  H01L29/74 ,  H01L29/786 ,  H01L31/09

Abstract: PROBLEM TO BE SOLVED: To provide a radiation detector formed by using a silicon-on insulator technology.
SOLUTION: The radiation detector comprises a silicon layer formed on an insulating substrate and having a PNPN structure, and a gate layer formed on the PNPN structure and having a PN gate. Latch-up occurs only in response to incident radiation in the radiation detector. In a second mode, the radiation detector has a silicon-on insulator PNPN diode structure and latch-up occurs only in response to incident radiation in the radiation detector. In a third mode, a silicon-on insulator radiation detector has a silicon layer formed on the insulating substrate, the silicon layer has the PNPN structure and a gate layer formed thereon, the gate layer has a PN gate, and latch-up occurs only in response to incident radiation in the radiation detector.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过使用硅绝缘体技术形成的辐射检测器。 解决方案：辐射检测器包括形成在绝缘衬底上并具有PNPN结构的硅层和形成在PNPN结构上并具有PN栅极的栅极层。 仅在响应于辐射探测器中的入射辐射时发生闩锁。 在第二种模式中，辐射探测器具有硅上绝缘体PNPN二极管结构，并且只在响应于辐射探测器中的入射辐射而发生闩锁。 在第三种模式中，硅绝缘体辐射探测器具有形成在绝缘衬底上的硅层，硅层具有PNPN结构和形成于其上的栅极层，栅极层具有PN栅极，并且仅闩锁发生 响应辐射检测器中的入射辐射。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：CA1191973A

公开(公告)日：1985-08-13

申请号：CA440689

申请日：1983-11-08

Applicant: IBM

Inventor： COTTRELL PETER E ,  GEIPEL HENRY J JR ,  KENNEY DONALD M

IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02

Abstract: ABS Process for Making Complementary Transistors A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.