公开(公告)号：CA1263716A

公开(公告)日：1989-12-05

申请号：CA507289

申请日：1986-04-22

Applicant: IBM

Inventor： CULICAN EDWARD F ,  PRITZLAFF PHILIP E JR ,  SCHETTLER HELMUT ,  VAN GOOR KENNETH A

IPC: H03K19/0175 ,  H03K17/60 ,  H03K19/013 ,  H03K19/018 ,  H03K19/088 ,  H03K19/082 ,  H03K19/092

Abstract: A circuit for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. The circuit has particular utility when employed with logic circuits such as "TTL" (Transistor- Transistor Logic) and "DTL" (Diode-Transistor Logic).

公开(公告)号：CA1229428A

公开(公告)日：1987-11-17

申请号：CA490346

申请日：1985-09-10

Applicant: IBM

Inventor： CULICAN EDWARD F ,  PRITZLAFF PHILIP E JR

IPC: H03K19/013 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03K19/088 ,  H03K19/173 ,  H01L27/02

Abstract: The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.